DSP Tools

[evgenia89]

Hello, Vitaly,

I implemented division with Divider Generator. Now I have a problem with compilation: the process Map takes about 2 hours if I include my model to the project (normally it took about 20 minutes). What can be a reason for so long mapping?

My Simulink model is attached.

Function precision is:

function z = precision(x)
    z = xl_force(x, xlSigned, 0);
end

 Function back_precision is:

function z = back_precision(x) 
    z = xl_force(x, xlSigned, 10)
end

 Function xlmax is:

function z = fifo_reset(x)
  if x == 511
    z = true;
  else
    z = false;
  end

Best regards,

Evgenia.

[vlavruhin]

Hello, Evgenia.

Well, your project is getting bigger.

Do you implement moving average filter for I/Q noisy signal? If so, then there are simpler ways to do it.

Also you can substitute MCode blocks by Reinterpret block ( for precision and back_precision functions) and Relational block (for xlmax function).

[evgenia89]

Hello, Vitaly.

Yes, I implement a moving average filter.
The description of Reinterpret block says that this block costs nothing in hardware. Can I still use it?

Best regards,

Evgenia.

[vlavruhin]

---

evgenia89 wrote:

The description of Reinterpret block says that this block costs nothing in hardware. Can I still use it?

---

Yes, you can. It costs nothing in hardware, because this block just says to System Generator to interpret that N-bits bus as number with binary point of your choice. But data samples are not altered in that case.

[evgenia89]

Hello, again!

The filter I am trying to implement is now working perfectly during simulation. But after FPGA configuration the output signal looks completely different from the input one. What can be a reason of this difference? And what can I do in this case?

Thank you for your help,

Evgenia.

[vlavruhin]

Hello.

---

The filter I am trying to implement is now working perfectly during simulation. But after FPGA configuration the output signal looks completely different from the input one. 

---

Could you describe your hardware setup? Are you trying HW-cosimulation? Are the inputs feeded from other FPGA blocks or from external hardware (ADC)? What is your sysgen clock? Software simulation of model is behavioural simulation only, i.e. it doesn't take into account all real route delays in FPGA. Make sure that you have defined all constraints properly.

[evgenia89]

Thank you for you quick response!

I am using ML605 with FMC150 daughter card.
I didn' try HW-cosimulation, I included the model to my main project and downloaded this to FPGA.
The inputs are feeded with FPGA blocks which are connected to ADC.

The FPGA clock in SysGen is 10 ns.

The signal I applying to ADC is ~100MHz.

I thought that it can be because I apllied the data type Unsigned_16_10 to GatewayIns and then I also reinterpret the data. But I have no idea how I can get to know which data type is in the signal after ADC.

Best regards,
Evgenia.