XST fails during synthesizing VHDL in AccelDSP

farshade · ‎12-20-2009

I try to synthesize a simple MATLAB code to VHDL as follows:

[Z, dZ] = accel_rdivide(A , B);

but during synthesizing RTL, I receiveg following error:

#=========================================================================
#* HDL Compilation *
#=========================================================================
#Compiling vhdl file "F:/testC/VHDL/XST/../test_div_package.vhd" in Library work.
#Package <test_div_package> compiled.
#Compiling vhdl file "F:/testC/VHDL/XST/../test_div.vhd" in Library work.
#Entity <test_div> compiled.
#ERROR:HDLParsers:164 - "F:/testC/VHDL/XST/../test_div.vhd" Line 2088. parser stack overflow
#-->
#
#Total memory usage is 146708 kilobytes
#
#Number of errors : 1 ( 0 filtered)
#Number of warnings : 0 ( 0 filtered)
#Number of infos : 0 ( 0 filtered)
#
#ERROR:Xflow - Program xst returned error code 6. Aborting flow execution...
#( E-SYNTH-0001): Synthesize VHDL with XST failed via return code.
# Explanation: Return value: child process exited abnormally
#
#( E-SYNTH-0001): Synthesize VHDL with XST failed via return code.
# Explanation: Return value: child process exited abnormally
#
#
#Synthesizing RTL design for language 'VHDL' using tool 'XST' FAILED
#( I-GENERAL-0001): Time elapsed: "7.30" seconds
#0

I have try this on 1-2 other PCs, and the same error appear.
all PCs benefit 2 GB RAM and 2 cores.
Xilinx version 11.1

shazni · ‎02-22-2010

Hello farshade.

I'm a newbie to this forum as well as to using FPGA. I'm here not to answer you question, but to ask you a question. Please solve this to me if you know. In AccelDSP I created a project and verified my .m script file and it when on normally. Then I clicked Analyze it goes on and stop with the following error.

#(        E-MAT-0001): D:\Designs\new_accel_DSP\gcc.m(0): Unable to infer the shape of 'for i.gcc.Variables.index'.
#        Explanation: The synthesizer was unable to infer the shape of the variable purely based on context analysis.
#        Remedy: Please add a zeros call at the beginning of the file to define the shape of the variable.

my script file is very simple and it is

x = [1 1 0 0 1];
y = [1 0 1 1 0];

tic
for i = 1:length(x)
[Y(i)] = gcc(x(i),y(i));
%disp(Y(i));
end
toc

My design function start off with

function [actual_direction] = gcc(k,m)

Is there any mistake that I've done in respect to above error? How can I solve this?

shazni · ‎02-22-2010

Hello farshade

I also get the same issue as what you had. Did you solve your issue in AccelDSP? You've posted this thread last year. You might have solve the issue. If so, could you please help me solve the issue. But my issue is slightly different, although most parts looks similar. The error message is as follows.

#ERROR:Xst:2001 - Width mismatch detected on comparator _old_mf_107_484/ALB. Operand A and B do not have the same size.
#-->
#
#Total memory usage is 460464 kilobytes
#
#Number of errors   :    1 (   0 filtered)
#Number of warnings : 10685 (   0 filtered)
#Number of infos    : 385 (   0 filtered)
#
#ERROR:Xflow - Program xst returned error code -1. Aborting flow execution...
#(      E-SYNTH-0001): Synthesize Verilog with XST failed via return code.
#        Explanation: Return value: child process exited abnormally
#
#(      E-SYNTH-0001): Synthesize Verilog with XST failed via return code.
#        Explanation: Return value: child process exited abnormally
#
#
#Synthesizing RTL design for language 'Verilog' using tool 'XST' FAILED
#(    I-GENERAL-0001): Time elapsed: "905.42" seconds
#0

I also see the following in the Generate RTL Report:

Under Performence Summary

Cannot calculate a constant throughput/latency for the design

Under Interface Configuration

Name	Value	Information
	Register Inputs	0	Inputs were not registered ( W-RTL-0022): Cannot register inputs and generate "push-mode" interface because the design does not have a constant throughput.
	Interface Protocol	full	Full handshake was implemented ( W-RTL-0022): Cannot register inputs and generate "push-mode" interface because the design does not have a constant throughput.

farshade · ‎12-20-2009

I couldn't solve the divider problem, so I decided to use System Generator Divider generated by CoreGen. it works fine.

About the first error you mentioned, this error usually happens while you are using variables with different fractional lengths. for example. if you have the code as following:

x = cos(y);

z = x * k;

and x is [47 45] and z is [53 50] (for instace), just try to change z to [48 45] to make its fractional length equal to x. i did it and it works.

About your second problem ("Cannot calculate a constant throughput/latency for the design"), this usually happens when you use a loop (such as For Loop) with variable number of iterations. For instance:

function y = test(x, L)

for i = 1 : L

y = x(i) * i;

end

as the number of iterations (L) is variable, "Generate RTL" cannot calculate the latency for the design. So, in the case such as System Generator Flow that the latency must be calculated, try known number of iterations.

For i = 1 : 100

y = x(i) * i;

end