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Visitor
deepanwita
Posts: 15
Registered: ‎11-28-2011
0

adc design procedure in Xilinx Sysgen 12.3

hi ,

i am working in sysgen 12.3.

i want to design simple ADC i.e i give some analog signal and want to find digital output. adc block is avalable in sysgen.

but ican not find the way to check the digital output. how i check the output of adc???? pls help me.........................

 another problem is---- when i put constant value as a input of adc block(idealized adc quantizer) and check the output through display, it gives a fixed value, the output does not depend on constant value, the output only depend on "number of converter bits" which is provide manually . as a example---- if set    "number of converter bits" = 12,  always give output in display is 4095,it does not depend on constant value. i attach wordpage of adc.   how i design adc in sysgen.. plz help me its urgent.....................plz

 

Xilinx Employee
austin
Posts: 3,649
Registered: ‎02-27-2008
0

Re: adc design procedure in Xilinx Sysgen 12.3

d,

 

The display is just telling you the result of 2^N (2^12 = 4096).

 

In simulation each simulator has its own method to check how the system works (supply data).

 

In a real system, a real signal (like a sine wave from a signal generator) is sent to the A to D converter to test it.  The output of the A to D is then acquired (saved) and transferred to a computer, where it can be analyzed for linearity, distortion, resolution, and so on.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Visitor
deepanwita
Posts: 15
Registered: ‎11-28-2011
0

Re: adc design procedure in Xilinx Sysgen 12.3

sir,

 

in xilinx system generetor  how i check the digital output.....................i.e means adc output.................

and how i give the input of adc i.e means analog signal....

Xilinx Employee
austin
Posts: 3,649
Registered: ‎02-27-2008
0

Re: adc design procedure in Xilinx Sysgen 12.3

d,

 

Look in the source and sink libraries, for sources, and sinks (displays).

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Xilinx Employee
Xilinx Employee
ywu
Posts: 2,861
Registered: ‎11-28-2007
0

Re: adc design procedure in Xilinx Sysgen 12.3

You may want to post DSP/SysGen related questions on the DSP Tools board: http://forums.xilinx.com/t5/DSP-Tools/bd-p/DSPTOOL 

 

You set your ADC block to accpet input voltage between 0 and 1. If you feed anything bigger than that, the ADC will just saturate and output the maximum quantized value. Try changing your input to something like 0.5 and see what happens.

 

 


deepanwita wrote:

hi ,

i am working in sysgen 12.3.

i want to design simple ADC i.e i give some analog signal and want to find digital output. adc block is avalable in sysgen.

but ican not find the way to check the digital output. how i check the output of adc???? pls help me.........................

 another problem is---- when i put constant value as a input of adc block(idealized adc quantizer) and check the output through display, it gives a fixed value, the output does not depend on constant value, the output only depend on "number of converter bits" which is provide manually . as a example---- if set    "number of converter bits" = 12,  always give output in display is 4095,it does not depend on constant value. i attach wordpage of adc.   how i design adc in sysgen.. plz help me its urgent.....................plz

 

 




Cheers,
Jim