11-30-2011 07:51 PM
i want to implement voice activity detection algorithm.
are there any support files for digilent atlys spartan6 fpga kit for system generator.
i am unable to configure ac97 audio codec.
i want to take audio 16 bit audio frames from "serial_data_in" port but i m unable to assign the port location in gateway in block that is "N18".... the issue is that input frame size is 16-bit long and gatewayin block is asking for 15 port locations (starting from MSB to LSB )
can any one guide me to right approach....
11-30-2011 10:40 PM - edited 11-30-2011 10:43 PM
you won't find any BSPs that support external Hardware access with HW-cosim (exept one outdated V2 or V4 board).
But Jimwu from Xilinx provided some useful information on that topic.
Find the link in this Posting:
Furthermore, the AC97 chip is connected via a serial interface, so you need some interface circuit that controlls that interface and provides the 16Bit data stream on the output. You can not connnect your 16 bit data port directly to the AC97 chip.
Have a nice synthesis
12-01-2011 03:50 AM
Did you have any luck with the AC'97 deserialisation code that I pointed you to in one of the many, many threads you've opened about this same design problem?
My understanding is that you'll need to create a black box using some HDL. You can use the Digilent code, but will need to modify it initialise the codec chip, reject incoming frames you don't care about, and spit out the 16-bit values using whatever interface System Generator expects.
Are you able to ask someone you work or study with, who is knowledgeable with HDL and System Generator, for help with this? We don't seem to be getting very far with helping you through the forum.