04-12-2012 06:47 AM
i've a question about the generic function in VHDL. Is it possible to use this function in sysgen ? if it's possible how can i do that in sysgen. Is there someone that know how to do that.
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04-12-2012 11:48 AM
entity counter is
generic ( width : integer := 7 );
port ( clk : in std_logic;
Q_out : in std_logic_vector(width downto 0)
Is it possible to realize such block in sysgen ?