DSP Tools

[batindeko]

Hi everybody,

i've a question about the generic function in VHDL. Is it possible to use this function in sysgen ?  if it's possible how can i do that in sysgen.  Is there someone that know how to do that.

Thanks

Olivier  

[austin]

b,

"generic" is synthesizable, or part of the languaqge, and yes, we support VHDL....hence we support generic usage.

[batindeko]

may be it's simple if i give an example.
entity counter is
generic ( width : integer := 7 );
port ( clk : in std_logic;
Q_out : in std_logic_vector(width downto 0)
);
end counter;
Is it possible to realize such block in sysgen ?

[austin]

b,

Are you coding in VHDL?  If so, yes.  If not, then I don't know.

[bwiec · Accepted solution]

Are you looking for the Black Box block in sysgen? Have a look in the reference guide.