DSP Tools

[randeel]

Helloeveryone,

I am using xilinx system generator. I generated my design for hardware co-simulation using that.

when i do that the clock that i am providing pass timing constraints without any problem for every path related to it,

but there is an internal clock called "dsp_clk" and timing related to those paths fail.

Can someone help me to acheive the timing in that path as well.

May be to decrease the clock(dsp_clk), currently it is 25ns. I am even not able to get a detailed report

of the failing paths in "dsp_clk" one either. I am using the gui to generate my design.

This is what i get.

* NET "dsp_clkibufg" PERIOD = 25 ns HIGH 50 | SETUP       |    -6.327ns|    31.327ns|      22|      136652

  %                                         | HOLD        |    -0.189ns|            |     512|       65280

* NET "dsp_clkibufg" PERIOD = 25 ns HIGH 50 | SETUP       |    -6.327ns|    31.327ns|      22|      136652  %                                         | HOLD        |    -0.189ns|            |     512|       65280

Thank you,

Best Regards,

Rana

[chrisar]

You can't change this because this is the actual clock on the board.

You might want to try opening a case with the Xilinx Technical Support to see if they can help track this down.

You can also try increasing the pipelining of your design to see if that helps with meeting timing.