parameters in sysgen blocks to ISE project

kchalla · ‎08-23-2011

Hi,

I have a model using xilinx sysgen blocks. As i want to have a flexible system, I have used variables in blocks parameters.

for example: "Count to value" and "Numer of bits" in Xilinx Counter, "Depth" in Single Port RAM..etc

I have generated the netlist files from the model and integrated in my project.

And now i m wondering can i instantiate these variables in my ISE project?

How flexible will be the parameters from Sysgen blocks? What is the better way to implement such a system? with System Generator?: or hardcoding in VHDL?

Any help will be needful.

Thanks in advance.

Best Regards,

Kiran

vlavruhin · ‎12-08-2010

Hi, Kiran.

I have generated the netlist files from the model and integrated in my project.
And now i m wondering can i instantiate these variables in my ISE project?

No, you can't. These variables are stored in MATLAB workspace. So System Generator gets values of these variables before HDL netlist generation and treats them as constants.

How flexible will be the parameters from Sysgen blocks? What is the better way to implement such a system? with System Generator? or hardcoding in VHDL?

There are two options as you stated:

1. SysGen-based. You can use variables in System Generator blocks. In order to be able to tweak them, you can change values of this variables and rerun HDL generation. This process can be automated from command line:

1.1. Create Matlab script file auto_generate.m in folder which contains your model:

% Put here all variables initialization
% var1 = ...
% var2 = ...

% open Simulink model named 'YOUR_MODEL_NAME.mdl'
open_system( 'YOUR_MODEL_NAME.mdl' );

% automatic click on Generate button of System Generator
xlGenerateButton( [gcs, '/ System Generator'] );

% close Simulink model without saving
close_system(gcs, 0);

% quit Matlab
quit

1.2. Execute created script from command line (in model folder) using following command:

sysgen -r auto_generate

2. VHDL-based. You should use VHDL generics in that case.

Which method is better? It depends on your preferred designflow.

Best Regards,
Vitaly.

kchalla · ‎08-23-2011

Hi Vitaly,

thanks for your reply.

For me the first option "auto_generate" is not good, as the customer should have matlab too to generate new netlist with the new variables....:(. And the variables are also changed in realtime.

Then I have left with the only option with VHDL generics.

Unfortunatly i invested more time in modelling the system and make it work. If i have to start the whole model in hardcoding in vhdl, then i have to start over again.

Is there anyway so that i can mix the generated netlist file with VHDL generics?

Thanks in advance.

Best Regards,

Kiran

vlavruhin · ‎12-08-2010

Kiran,

For me the first option "auto_generate" is not good, as the customer should have matlab too to generate new netlist with the new variables....:(.

Well, Matlab variables will be useless in that case.

And the variables are also changed in realtime.

Changed in realtime? What do you mean? Could you elaborate on this?

Unfortunatly i invested more time in modelling the system and make it work. If i have to start the whole model in hardcoding in vhdl, then i have to start over again.
Is there anyway so that i can mix the generated netlist file with VHDL generics?

Since you're getting HDL netlist after generation from System Generator, then you could try to figure out where and how the parameters are used and create HDL wrapper with generics.

Best Regards,
Vitaly.

kchalla · ‎08-23-2011

Hi Vitaly,

thanks for your reply.

And the variables are also changed in realtime.

Changed in realtime? What do you mean? Could you elaborate on this?

Example:

For the changing receive window length, the amont of incoming data for a frame changes. If i have a buffer for incoming data for window length size, then my address encoder for RAM and depth of RAM parameters should fit according to the receive window. The user has the option to change the Rx Window length.

I hope you got it what i mean...:)

I have already generated the HDL netlist.

Do you mean creating HDL wrapper with generics means editing the generated *.VHD file and connecting the generics to the variables at the top level?

I m doing it first time. so i m confused.

Thanks a lot for your help.

Best Regards,

Kiran

vlavruhin · ‎12-08-2010

Hi, Kiran.

Example:
For the changing receive window length, the amont of incoming data for a frame changes. If i have a buffer for incoming data for window length size, then my address encoder for RAM and depth of RAM parameters should fit according to the receive window. The user has the option to change the Rx Window length.

I hope you got it what i mean...:)

Well, the question is whether this change should be done on-the-fly in the FPGA or it could be implemented in different netlists and bitstreams? In former case, you can set all parameters to the maximum values and change them using additional ports for current values (Gateway Ins). For example, RAM's depth can be set to the maximum window length size but addresses can be restricted to less memory space using external parameter.

I have already generated the HDL netlist.
Do you mean creating HDL wrapper with generics means editing the generated *.VHD file and connecting the generics to the variables at the top level?

Yes, you could try to do so if the change of the parameters means having different bitstreams. But it can be hard work.

Best Regards,
Vitaly.