06-20-2011 11:00 PM
Thankx in advance.
I am using Xilinx's ISE 11.4 with Matlab system genrator 11. I am implementing an algorithm using Xilinx's Virtex 4(XC4vsx35). While doing algorithm implementation, few steps are done. I got expected results. but now I am stuck up with just a multiplication operation. Previously it is done with the same algorithm. I tried different operation like addition etc. If I am using a variable for multiplication or addition its not showing result. like:- matout=2*k;
but if I will use constants like matout=2*2;, It shows result.
I am using verilog for implementation.
I am not getting what is the issue.
06-21-2011 12:44 PM
What do you mean by "its not showing result". If Synthesis passes, I would suggest you check the function correctness by running simulation.
Not sure about the System Generator part of your question. To me it is more like a System Generator issue. I'll move it to the DSP Tools board. If Synthesis is doing anything wrong, please isolate the Synthesis problem and post it on the Synthesis board.
06-22-2011 11:47 PM
I am using ISE as a development platform foe programming and system generator to simulate the programm.
Algorithm that I am implementing is big one. That's why, I am doing it step by step.
Few of the steps are implemented and tested with system generator successfully. Now I am stuck up at one step where I am not able to perform just a simple operation that is multiplication. In the previous steps multiplication is already performed.
With troubleshooting of this issue I tried follwing things:-
1. used intermediate register to store and then tried to do multiplication
2. tried to do multiplication in next clock cycle
3. checked for other operation like addition. Addition is also not showing simulated output(in sys gen)
These are few lines of verilog code where I am stucked.
"oneby" is a function that perform certain operation. I am getting expected value in register "matrixk[k]"
"kaldns" is just an intermediate register used.
and matout is output port which I am looking over in system generator.