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03-03-2012 12:59 AM
A project contains synchronization reset and asynchronous reset,is it right? Thanks!
03-03-2012 08:41 AM
An FPGA has both kinds of reset. Any particular project may use one or the other or both.
You might want to read this blog:
http://forums.xilinx.com/t5/PLD-Blog/That-Dangerous-Asynchronous-Reset/ba-p/12856
-- Gabor
