04-09-2012 03:07 AM
Hi respective members,
Im using ise design suite 8.2i, I have created an IP core block named as "sram64kdata" using block memory single port. I already instantiate the "sram64kdata.v" in the design and add the instantiate template in top module and declare the ports.
But realized that there is "BLKMEMSP_V6_2" that need to instantiate below "sram64kdata.v" module, which I realized not obtain in the folder where the the output file for generate block memory single port of sram64kdata. Do I have to create this file?(pls refer below)
pls do help me.
Thanks in advance.
Solved! Go to Solution.
04-09-2012 08:46 PM
no problem occurred when synthesizing n implementing the design. but the result is not in what expected. supposedly,the data in program memory will executed but fail.
04-10-2012 12:06 AM
If Synthesis and Implementation completes successfully, your design problem (saying the result is not what expected) is not caused by the "missing file". Are you using VHDL lanuage? When using VHDL, a question mark in front of a source file (missing file) is allowed as long as the netlist file of this source can be found by Translate.
04-12-2012 03:40 PM
Yes, the same applies to Verilog as to VHDL. As Vivian stated, as long the netlist (ngc) is found by Translate (check then Translate Report (.bld)) to ensure the .ngc file was added, then the problem is not caused by the “missing file”.