05-03-2012 11:51 AM
I'm working on a project where we have one generic CPLD design, which will be continually rewritten with different values. The verilog file used will be the same layout for example, but key values need to change between each CPLD my company will be designing. For this reason, we need to synthesize, fit, etc everything via command line.
I have our demo project, which I've tested in the ISE GUI interface. Now, I'm trying to perform all the steps through the command line using this documentation:
Initially, I've tried to map through so we can use the following command to attempt to run the process with XFLOW:
xflow -p XC2C128-6-VQ100 -fit balanced.opt C:\ProjectFolder\ProjectName
Which works up until the point where it calls hprep6, where I see this error:
#Starting Program hprep6
#hprep6 -i ProjectName -r jed -s IEEE1149 -a -l ProjectName.log -n ProjectName
ERROR: Portability:90 - Command line error: Switch "-r" is not allowed
I'm using Xilinx tools 13.2. The documentation does not outline any -r command for hprep6, is there any way to change my options to not include that command? It's continued to stop the process.
Thanks in advance for any help
Solved! Go to Solution.
06-12-2012 04:05 PM
One thing you could try is to run the Project Navigator flow once and then open the Command line log under Design Utilites.
The file should look similar to the following and can be easily saved as a batch file to execute all of the commands repeqatedly.
xst -intstyle ise -ifn "C:/cases/13/jc2_ver/jc2_top.xst" -ofn "C:/cases/13/jc2_ver/jc2_top.syr"
ngdbuild -intstyle ise -dd _ngo -uc jc2_top.ucf -p xc9572xl-CS48-7 jc2_top.ngc jc2_top.ngd
cpldfit -intstyle ise -p xc9572xl-7-CS48 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper jc2_top.ngd
tsim -intstyle ise jc2_top jc2_top.nga
taengine -intstyle ise -f jc2_top -w --format html1 -l jc2_top_html/tim/timing_report.htm
hprep6 -s IEEE1149 -n jc2_top -i jc2_top