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Generated core causing problems in par (ProjectMg mt warning)
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05-02-2012 08:21 AM
I inherited a project that was started in 13.2, but I am currently running 13.4. The project will Synthesize and everything fine, but as I look at the console,
I am getting a steady stream of: WARNING:ProjectMgmt - File Z:/blah/blah/blah/coregen/icon.vhd is missing
icon1 is a ICON core that was originally made when in 13.2. Looking at the setting for it, it says that it is Verilog (which I want), so I don't know why it is looking for a .vhd file. I tried regenerating the core, but that doesn't solve the problem. I grepped for what is calling icon1.vhd, but couldn't find that in any of the project files. When I start up chipscope, it claims to not see any cores, so I have a feeling it is related to this problem.
How to I clean this up so it doesn't keep choking on this?
Thank you!
Re: Generated core causing problems in par (ProjectMg mt warning)
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05-02-2012 08:20 PM
Are you able to run the design through Synthesis, Implementation and Bitgen successfully? If so, this warning is not the cause of your chipscope issue.
I suggest you go to "Design Tools - Others" board, open a new post and describe your chipscope issue in detail (error message and etc.)
Vivian











