Design Entry

[jnurmine]

What would be the best way to go about packaging my own design to a "black box" so others can drop it into their system but not be able to see and copy/alter the contents? I've tried to find documentation about it unsuccessully.

[tmcdowe]

This is not a documented or supported flow, but it can be easily done.  It just takes some understanding of how the ISE tools work under the hood.

During synthesis (XST), if there is any module that does not have corresponding HDL source code (or a schematic for schematic designs), XST will blackbox that module with the expectation that NGDBuild (translate) will find the body for that module in a netlist somewhere.

You can leverage this behavior to your benefit by synthesizing _just_ the module which you would obfuscate (by itself as a top-level module and make sure that you turn off automatic IO buffer insertion when synthesizing this module).  This will create an NGC netlist for this module.

Then, in your design, simply instantiate the module with no corresponding HDL/schematic backend and run through XST.  You should see a message from XST that it is blackboxing the module.

Then, in NGDBuild, simply use the -sd flag to tell NGDBuild where to find the NGC for the module.  NGDBuild will stitch it into the monolithic netlist and you're good to go.

This doesn't encrypt the netlist, but it certainly doesn't give access to the source.

[dguisinger]

As a follow up to this question, is there a way for someone other than Xilinx to distribute a blackbox core that is encrypted?

I've got a core I've been working on which I'd like to have demonstration cores and fully licensed cores, and am looking for the proper way to lock it down for both synthesis and simulation.

[tapgrant]

And I am interested in doing that

[cosanzeana]

I've tried to instantiate the module with no corresponding HDL backend but I get an error when I try to run through XST...

[howardp]

Verilog requires a module declaration for an instantiated ngc file.  Just create a wrapper HDL file for the NGC.

There is an old Article (http://www.xilinx.com/support/answers/11132.htm) on how to do this for Schematics.  You could use the information from the article to create a .v or .vhd for the NGC file.  Then just add the .v or .vhd to the project and ignore rest about the schematic instantiation.