Design Entry

[goodspeed2009]

When implementing my algorithm, I have used both the embeded  multipliers and the IP Core of Multipliers. In my opinion, all the multipliers are implimented in FPGA .That is because the embeded multipliers are embeded in FPGA and the  IP Core of Multipliers are implemented by LUT. Why they have occupied so many IOBs?

How can I reduce the usage of IOBs? Could you give me some advice on the IOBs?

[woutersj]

Do you have some code so we can see what could be going on?

My first guess would be that you have a number of inputs and outputs on your design. These will be connected to pins (IOB) by default/. If you don't want this to happen, you have to tie them to something in your design.

Cheers,

Johan

[eilert]

Hi,

if you are not designing a top-level module, you can deactivate the "Add I/O-Buffers" option in the XST Synthesis options.

If you are going to implement that design anyway, you either have to add I/O Buffers manually or let the translate/map stages do it for you.

Have a nice synthesis

  Eilert