03-03-2012 01:01 AM
Checking the syntax on the simplest of VHDL modules is for some reason always generating an info message for me now. I'm using the text editor with ISE 13.4, and here's what I've boiled things down to:
entity frob is
rdata: out std_logic;
wdata: in std_logic
architecture bogus of frob is
rdata <= wdata;
The info message is:
INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL
Is there something "behind the scenes" that is making xst unhappy for real, or is this just a red herring message that shouldn't really be there and can be safely ignored?
I consider it bad form to simply ignore griping from the tool chain, but I'm stumped as to how to make that message go away. Can someone please shed some light on this one for me?
03-03-2012 07:56 AM
Since there are no part selects in the code you posted, either your project has some lingering
stuff that you don't see (try cleanup project files) or the info is generated by something in the
std_logic_1164 library. You could try a different library to see if the info message persists.
Xilinx is not particularly good at removing code that creates info or even warning messages
once they have a package that (mostly) works.
03-03-2012 02:44 PM
I created that code in a new empty project before testing it, which should eliminate the possibility of lingering junk hanging around in the project files I would think. As for the library being at fault, I just created another new project with one Verilog file containing the following:
module boink( input a, output b );
assign b = a;
It also generates the info message. I have to assume it's not related to anything I'm doing (or not doing), and is either caused by some error internal to xst or the related support files, or perhaps the error is that the message is generated when it shouldn't be. This just started when I installed 13.4, I don't recall ever seeing this message with 13.3 before.
Maybe Xilinx has contracted with the Psychic Friends Network, and the tools know that some day in the future I will botch a part select index so they're trying to pre-warn me... ;-)
Is anybody else with 13.4 seeing this, or am I just special? I don't really want to back-date to 13.3 if I don't have to, then again the threat of some error I can't see leading to "incorrect synthesis" doesn't sound like a lot of fun either.
03-03-2012 07:22 PM
Possibly not helpful, but I never use the "check syntax" feature of ISE.
I don't even bother trying to synthesize until my code simulates and verifies. So at least I know that it'll compile without complaints.
Yes, I do this for a living.
03-03-2012 07:35 PM - edited 03-03-2012 07:36 PM
Well, not harmful. ;-)
I just use check syntax as one of the steps before simulation to help catch typos and other such personal stupidity. I've found that even the simplest code can contain subtle errors so I simulate every module individually and again collectively as I move up in the design hierarchy. It can be tedious, but it's a far sight better than staring at a board wondering why it's not doing what it's supposed to.
Maybe I'm just too [was going for ay-nal retentive, except I got bleeped so I'll go with obsessive], but I don't like any griping at all from the tool chain. Especially spooky vague references to incorrect synthesis...
03-03-2012 07:36 PM
I probably missed the "check syntax" bit of the original post. Do you get the same
info messages if you go straight to synthesis rather than check syntax? I also rarely
use "check syntax" because I've found that it misses a lot, and it gets confused when
there is conditional code generation (tries to check syntax of parts that aren't included