Design Entry

[rosalba_zarate]

Hello,

I am using verilog Xilinx ISE 13.2 (nt64). 

My problem is that when I finish to synthesize my project I don't obtain the "Summary repor viewer" automatically. In fact, when I click on sigma symbol of Design Sumary/ Reports I never obtain the report viewer. When I click on Design window/Synthesize-XST/View Text Report I can see the plain text of synthesis results. But I prefer "Summary report viewer" which appears always empty with no information.

I think this happened because in the beggining my problem was that I was obtaining the synthesis results for an old project, but no the new project I was running. So, I use the Source/Cleanup Project Files because I tought this would solve the problem. But when I synthesize the project I want, the report viewer appear forever empty.

Any idea?

I attached a screen-shot of my empty viewer report.

I also post my Syntesis Messages because maybe they are related with my problem. I am not sure...

Synthesis Messages

lun 30. ene 12:22:36 2012

---

	Synthesis Messages - Errors, Warnings, and Infos	New
INFO	Xst:2117 - HDL ADVISOR - Mux Selector <state> of Case statement line 467 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can: - add an 'INIT' attribute on signal <state> (optimization is then done without any risk) - use the attribute 'signal_encoding user' to avoid onehot optimization - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
INFO	Xst:738 - HDL ADVISOR - 1024 flip-flops were inferred for signal <bnds>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
INFO	Xst:738 - HDL ADVISOR - 1024 flip-flops were inferred for signal <bnds>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
WARNING	Xst:646 - Signal <fixed<31:16>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING	Xst:646 - Signal <fixed<-17:-32>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
INFO	Xst:3226 - The RAM <Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s):
INFO	Xst:3226 - The RAM <Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s):
INFO	Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

[bwade]

You are describing a problem with Project Navigator displaying the design summary. It would be better to discuss this at the Design Entry forum which also covers Design Management issues related to Project Navigator.

[eteam00]

If you look in your project file nnnn.xise, there may be a reference to your old project name.  This will cause the symptoms you describe.  It's a text file, so it is easy to scan and edit.

-- Bob Elkind

[howardp · Accepted solution]

The design summary will not be updated with the correct reports if for some reason the selected top level module in the project is not the same as the module Design Summary is looking for.  Check out http://www.xilinx.com/support/answers/39597.htm for more of an explanation and a way to fix the issue.

[rosalba_zarate]

I changed all my .v files to another route and add these files to a new project. That was the only solution I could apply.  As the link of "Project Navigator - Some items in Design Overview/Detailed Reports are greyed out" says I changed many times top level that was the cause of my problem, but I needed to do that. 

Thank you eteam00 and howardp.