Design Entry

[sweetpotato]

Hi,

I want to implement  the AXI-Stream FIFO via fifo generator (Core Generator).

After the FIFO was generated, I can't find any simulation model or testbench in the project.

Xilinx doesn't provide it or I need to manual download it in AR?

ENV: ISE 12.4, FIFO Generator v7.2

Thanks in advance!

[luisb]

If you generate the core within ISE I would look in the ipcoredir directory for the simulation model.

If CoreGen is not generating the model for you, then simply take the NGC that it generates and run NetGen to create a structural model.