Design Entry

[ehsankh88]

Hello.

 i have designed a microblaze processor and now I want to add an osd IP (ON screen Display) to my microblaze as a peripheral.

So I opened a new project in ise and created osd ip core. But when I double click to view HDL Instantiation Template this error appears (whether i choose vhdl or verilog) :

The instantiation template corresponding to this core does not exist. Either the core does not provide it or he core is not up to date with respect to the ise project setting.

This core has a lot of  ports, so it is too difficult to type components port map.

Thank you.

[viviany]

Please attach your ISE project in which you created the OSD IP core.

Thanks,

Vivian

[ehsankh88]

Thank you for your answer.

I hase the same problm with MIG ip core . but it works when i choose verilog.

[howardp]

During the generation of the MIG core, you should have seen a message the VHDL was not supported.

Project Navigator will look for the <core_name>.vho for VHDL or <core_name>.veo for Verilog.  If the file corresponding to the selected functional language does not exist, Project Navigator will issue the error mentioned.

If the file does not exist or cannot be created through CORE Generator, one work around is to temporarily replace the core with the top level HDL module and run the "View Instantiation Template" process for the HDL.