04-10-2012 04:45 AM
I've instantiated a number of FIFOs using a for generate statement. I'd like to constrain where those FIFOs are placed using the LOC constaint in my .UCF file but I don't know how the modules are named using when the "for generate" statement is synthessized.
I'm looking for something along the lines of:
INST <module name>/<sub module name>/gen_fifos[i] LOC = XXX;
where I don't know exactly how gen_fifos[i] really gets named.
Any ideas how I could find the proper names?
gen_fifos : for i in 0 to 9 generate
meta_fifos : fifo_32x32
port map (
RST => fifo_reset,
WR_CLK => CLK,
RD_CLK => FIFO_BUS_IN(i).fifo_clk,
DIN => DP_BUS_IN.dp_mem_d_out,
WR_EN => running,
RD_EN => FIFO_BUS_IN(i).fifo_re,
DOUT => FIFO_BUS_OUT(i).fifo_data,
FULL => fifo_full(i),
ALMOST_FULL => fifo_almost_full(i),
OVERFLOW => open,
EMPTY => open,
ALMOST_EMPTY => FIFO_BUS_OUT(i).fifo_almost_empty,
UNDERFLOW => open,
SBITERR => open,
DBITERR => open
end generate gen_fifos;
Solved! Go to Solution.
05-14-2012 08:11 AM
I had the same problem and then remembered that one way you can get the instance name using the ChipScope core inserter.
When you are on the Select Net page, you can use the filter to find your net, and then it shows you the instance name of the source for the particular net. Note that nets sometimes change name or get optimized away by synthesis.
In general for VHDL, the instance format is:
<component label>/<component label>.../<Generate Label>[<generate index>].<component label>
05-14-2012 07:26 PM
This (finding instances names) is one of the things what PlanAhead does the best. Just open the netlist or synthesized design you will be able to see names for all objects (instances, nets, etc).