Hi everyone,
I inherited a PlanAhead project and need to document a few things with it. I'm using 13.4.
There are a bunch of VHDL files that aren't used by the top-level design. However, they still show up in the list of files, since they have been imported as source into PlanAhead. Is there a way in TCL to show the list of "active" files, i.e. stuff that makes it into the modules heirarchy? I need to script this up because doing it manually will take a while, there are a lot of files and VHDL libraries as part of the PlanAhead project.
Thanks for your help!
