Design Planning

[anupkini]

Hi All,

I get the below mentioned error when i try to implement a run in PlanAhead 13.2.

[Place 864] Incompatible IOB's are locked to the same bank 36
Conflicting IO Standards are:
IO Standard 1: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = INPUT, DRIVE_STR = NR
List of locked IOB's:
button_start
button_stop

IO Standard 2: Name = DIFF_SSTL15, VREF = NR, VCCO = 1.50, TERM = NONE, DIR = OUTPUT, DRIVE_STR = NR
List of locked IOB's:
fpga_0_DDR3_SDRAM_DDR3_Clk_pin
fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin

These IO Standards are incompatible due to VCCO mismatch.

I have a DDR3 MPMC in my system along with MicroBlaze.

I am using a ML605 - Virtex 6 board with ISE 13.2

Kindly let me know how ot proceed on this error .

Thanks,

Anup.

[gszakacs · Accepted solution]

According to ug534, the user push-button switches use 1.5V so they should have an IO Standard

of LVCMOS15, not LVCMOS25.  Make sure that you are using the .ucf file that comes with the board,

and if you have changed any signal names, make sure that the names are changed in the .ucf

file to match the design names.  Note that a board-level signal can have more than one constraint

in the .ucf file.  Most have at least a LOC and an IOSTANDARD constraint.  If you don't constrain

the IOSTANDARD, LVCMOS25 is the default.

-- Gabor

[anupkini]

Thank You Gabor.
It worked !

Let me know where you looked up for the IO Standards. I was unable to locate valid keywords for push button or DDR# pins.


regards,
Anup.

[gszakacs]

I just searched ug534 for "button" and found a schematic on page 51 that shows the button

tied to "VCC1V5", which usually indicates +1.5V.  However, I would normally expect the .ucf

file delivered with an eval board to have valid LOC and IOSTANDARD constraints for any user

I/O pins.

-- Gabor