Design Planning

[chobeika]

Hello,

I'm not so familiar with PlanAhead but I want to use it cause I believe it can solve my problem.

I have a design let's call it : design1 that I implemented with project navigator. So I got the RTL design1.ngc and design1.ncd.

I'd like to implement a new design (design 2) that will contain an instance of design 1 and an instance of another design: design 2.

What I need is to keep my design1 with the same placement and routing that were done with ISE project navigator (design1.ncd).

How can I do that ?

Can we do the placement in several steps ? Is there a way to import the design1.ncd to lock it and then add up other modules (design 3).

Thank you for your help,

Christelle

[woodsd]

PlanAhead is a very powerful tool and provides many capabilites in IO planning, floor planning, and design analysis.  However, it calls the same implementation tools (ngdbuild, map, par) as Project Navigator.  What problem are you trying to solve with it?

It sounds like what you need to do is to create a new top level (verilog or VHDL) that instantiates the two designs.  These two designs can be black boxes at synthesis, and then you will provide the NGC files (design1.ngc and design2.ngc) to the implmentation tools.  This is all relatively straight forward, and planAhead doesn't necessarily buy you much here unless you need to floorplan or do pin planning on the new design.

For the second issue of maintaining the same placement, this is not easily done.  I think the big question here is why? There are hierarhical design flows that can be used to accomplish what you want (Design Preservation, Team Design), but you have to plan for this from the start.

If you can provide a few more details about what you are tyring to do it may be possible to provide some more guidance.

[chobeika]

Thank you for your reply.

I tried to create a top with black boxing my design1 but I got this error when synthesizing:

Port <clock> has illegal connections. This port is connected to an input buffer and other components

I guess this is because the synthesis of my design1 was done without disabling "add I/O buffers". And I can't redo my synthesis because I need the same exact files that were used in an experiment.

Actually we have bombarded the board with design1 on it, with protons and neutrons and got some results in terms of sensitivity to SEUs. We know the exact addresses that were flipped.

We need to recreate the same results using the SEU controller by emulating SEUs at the same addresses. In order to get the same results I need to place the same synthesized design where it was during the bombardment at the same placement and add up the SEU controller. Unfortunately this wasn't planned from the beginning.

Do u think design preservation can solve the issue? From what I read I'm not quite sure.

Is there any possible way to do this ?

Thank you again for your time

[woodsd]

If the lower level blocks (design1 & design2) have IO buffers, then you need to disable IO insertion for the top level synthesis.  You can do this globally with the synthesis option, or port by port by adding an attribute (XST is BUFFER_TYPE=NONE, and synplify has something similar).

It sounds like your only option at this point to preserve the placement is to extract the placment information.  You can load design1 into planAhead by creating a "post-place and route" project.  This will ask you for the netlist (NGC), Physical design (NCD), and a constraints file.  You can then open the Implemented design and view the placment results.  Finally, you can write out all of the placment information to a UCF.  The exact method for this varies a bit depending on the version of PlanAhead you are using, but this should be close:

 1. Create a post implementation project and open the implemented design view

 2. Export the constraint (File-->Export-->Constraints)

 3. Uncheck the box that says "Export fixed location constraints only (this will tell planAhead to write out constraints for every instance in the design).  This will write out LOC and BEL constraints for each instance, so the file will be large.

You will then have to modify the names in the exported UCF to match your new hierarchy.  If you instantiate design1 as "u_design1" then you will need to add a "u_design1" to the front of all of the instance names.  

The downside to this is that the tools are really designed to have the entire design locked down, and you may see some poor performance.  Also this is only going to lock down placment, and not routing!!  

Using partitions would give you the solution you need, but you would have to reimplement design1 and design2 with partitions first.  

Good luck!

[chobeika]

Thank you so much.

I'll try that

christelle