Design Planning

[airturk]

Dear Members;

I have a vhdl design and I am targeting a spartan6-slx150 using the ISE 12.4 toolset.

My question is related to pinout assignments and running the Noise Analysis tool using PlanAhead.

I run the planahead after the synthesis and perform DRC. The tool is happy and there are no error. 

After I run the noise analysis, and then I see that the I/O Bank 0 fails the test with -55% remaining margin. 

I think the solution to that is changing the IO Standard, or drive strength or off-chip termination, or moving some of the pins to another, less utilized, bank. I completely agree with all these solutions. 

However, I really like to know how the tool figures out the load on these pins. Currently, I have 31 outputs, including Host Port, Master SPI, Slave SPI, GPIO lines, and JTAG. BUT, I know ~8 of them are used only in the startup, some of them are GPIO lines are used very infrequently. 

How does the tool account for this?

Any insight, recommendation is appreciated.

Regards, 

[tanders · Accepted solution]

Device limits are listed in the UG:

http://www.xilinx.com/support/documentation/data_sheets/ds162.pdfhttp://www.xilinx.com/support/docum...

For the calculations, there are many factures, including but not limited to: The bank, pwr/gnd pins, port/pin location, IOStandard, Drive, Termination, etc...  Ealier versions of software used a more conservative analysis that did not look at pin/port location.