Design Planning

[283420]

So woodsd, I had look again at all the reports and indeed no errors/warnings...

Two things I now noticed/realized:

1. The missing components in PlanAhead are only LUTs(not all of them) actually... Why? I also found this Warning Message in PlanAhead:

"WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings."

2. For example: I have a 3 bit binary Counter. The three Flipflops are actually placed in PlanAhead. When I right-click on one of them and click "Show Connectivity" it does not even show the Clock-net that drives them... (Though when I click on the BUFGP of the clock that is driving them, and go to the output net, PlanAhead actually shows a connection to the three Flipflops... Not very user-friendly in my eyes...)

But far more important: It does not show the D-Input of the Flipflops... So I thought, this CANNOT be...
So I switched to FPGA Editor and searched for the same SLICE X "" Y "". And voilà it showed me LUTs and Data Connections and everything... So is it maybe, that PlanAhead does not show Connections inside the Slices AND that probably the LUTs that were originally synthesized for the counter logic were optimized so that a completely new set of LUTs resulted, which therefore are no more shown in PlanAhead but only in FPGA Editor?

Sorry for the mass of questions... Really trying to understand all this...

Also another (short) question I would have (bit off topic...):
Can you define OFFSET In (Hold-/Setup-Time as far as I understand...) Timing constraint for bidirectional signals?
Seems like it always gives me errors/warnings when doing that...

Thank you a lot!
Gilles

[woodsd]

I'm not the best person to answer all of these.  Most of the questions you have answered yourself, and you seem to have a good understanding of what is going on.  The warning from XDL may be due to the switches that PlanAhead uses when calling XDL, or may be just a limitation of XDL in general.  I'm not 100% sure on that.

In order for planAhead to show the physical design, it has to try to relate the logical the optimized physical design, and use tools like ngc2edif, XDL, etc. in the process. This does introduce some limiations on what it can show unlike FPGA Editor that can just read the native physical database.  Also, PlanAhead doesn't show routing (just ratsnets), and I'm not sure what the limitaions of this are.  We may not show clocks nets by default, and you are correct that we can't diplay inter-slice connections.

In our next generation of software (Vivado Design Suite) these kinds of limiations have been addressed. 
http://www.xilinx.com/products/design-tools/vivado/ 

[woodsd]

For OFFSET constraints, these are supported for bidirectional IO ports. You obviously define the OFFSET/IN on the input side, and OFFSET/OUT on the output side.  If you are getting errors, you may want to search the answer database for these errors and see if you can find a solution.  

[283420]

Hello everyone!

I am close to finishing the project. However for demonstration purposes I would still like to show the whole final physical design within the fpga with a nice and representative screenshot. Is there any other (freeware-)tool I can use to show my physical desing in a visual way?? Because still planahead does not show any LUTs which makes the fpga seem very emtpy although it isnt...

Please help!

Thanks!

Gilles

[woodsd]

PlanAhead should show LUTs.  The limitation with PlanAhead is that it connot show anything in the physical design that it cannot find in the logical design.  

If you want a full representation of the physical design, open the placed or routed NCD in FPGA Editor.  You can launch FPGA Editor from PlanAhead, or standalone. 

[283420]

Well my PlanAhead only shows the LUTs of the IP Cores but not these of my self-programmed components... did I forget to adjust a certain property within the design flow or.....?

Also: have you noticed that there is a very annoying bug in PlanAhead-Device View, that two Clocking Regions always shrink every time you zoom so that after maybe 10 zoom operations two clokcing region-frames have disappeared? is this solved in 14.2? (downloading it right now...)

or does vivado give me a better way to show my physical design??

and if: where can I get a license for vivado/which licenses work for it? Webpack License?

Thanks

[woodsd]

I'm not sure what you mean by self-programmed components, but I don't think there is anything you did or didn't do to affect if these components are visable in the device view.  

I haven't noticed that bug in PlanAhead.  Hopefully 14.2 fixes it.

Vivado have a similar device view to planAhead, except you can see much more detail and switch to a routing view that shows all routing resources.  This is full replacement for FPGA Editor (and then some). With that said VIvado is 7-series only (not sure which device famility you are targeting), and you would have switch your entire design over to XDC constraints.  However, because Vivado is directly reading/managing the database, you should be able to see a full representation of the implemented design in the device view.

If you haven't used Vivado yet, I would suggest trying it out.  It's a lot of fun.  I can't help on the license front, but you shoudl be able to request a webpack type license.  If you have a full license for 14.2, you should just get Vivado with it.