I'm using PlanAhead just to get initial pin planning location constraints defined for a complex LX110T design that includes a PCIe core. The coregen constraints locating the GTX modules are correctly assigning the data lane I/O pad locations. However the IBUGDS and pad locs associated with the RCLK inputs are being rejected as illegal by the floorplanner. It will also not let me manually assign those pins to the appropriate GTX module pins.
Is this just a PlanAhead bug, or is there some particular I/O standard (besides the default LVCMOS25) that needs to be given to the RCLK inputs to allow them to be placed in the GTX block?
