Design Planning

[puxiangjun]

HI:

   follow is my planahead project, "sol_top_ext_shared.ngc"file include IODELAY module.

 When i excute " implemented design" in planahead,and then will generate a complete EDIF netlist in <projectname>.runs. I open this edif file,I found the "IDELAY_VALUE" disappered when I set this value is greater than 32, please see below pic:

              picture 1: IDELAY_VALUE is greater than 32, it's disappered



 picture2: IDELAY_VALUE is less than 32.

    So,the project is failed, The Idelay is no any effect when i download bit file into virtex-5 fpga.Why?

[woodsd]

If you check the Tcl Console, is a message (CRITICAL_WARNING or similar) written out regarding this constraint?  It seems like PlanAhead may have had an incorrect check on this value on expecting it to be 0-31.

It would be best to check this in a 13.x version of planAhead.  If you don't have access to this you could create a webcase and work with support to see if this as been fixed.  

To work around this issue you can set this propery in the UCF (see the cosntraitns guide):

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/cgd.pdf

Make sure the UCF constraints ends up in the <projectname>.runs/<run>/<run>.ucf.  If planAhead is dropping the UCF cosntraint as well, then add this to a separate UCF, do NOT include it in the PlanAhead project, and feed to NGDBuild by adding a "-uc" switch under "More Options" in the PlanAhead strategy.