Design Planning

[yavv]

Hello!

After upgrading PlanAhead from 13.4 to 14.1 i've got very annoying problem.

Every time I'm running implementation (or simply opening Synthesized Design) PlanAhead hangs while reading UCF constraints (even if the UCF file is empty).

It displays "Reading file xxxxxxx.ucf" dialog and hangs at 0 percents. If I press the "Cancel" button it says "Canceling, please wait", and this dialog remains on the screen forever. The only way to close it is to kill the PlanAhead process via Task Manager. The PlanAhead process eats 100% of the CPU core at this time.

The same situation is on Windows and Linux machines. I've tried to update Java JRE used by PlanAhed to latest version but there is no any effect. There is no anything in PlanAhead's log files (even if it runs with genLog/genJournal options).

The problem persists with new designs after some "Synthesize"-> "Implement" runs. It works ok two to five times then hangs again and again.

PlanAhead 13.4 works well with same projects.

Any ideas?

[vladimir777]

Why Xilinx developers are so quiet? I have exactly the same problem.

[tanders]

Several loading issues have been fixed for 14.2, which will be released shortly

These issues are typically design/data specific, so I would recommend filing a WebCase http://www.xilinx.com/support/clearexpress/websupport.htm to get the fastest resolution.

[yavv]

The problem is NOT project-related.

I'm creating new empty RTL project for the XC6VLX75T fpga. Then I'm adding new empty VHDL file, writing an empty entity/architecture with one-two signals, and adding empty UCF to the project (with no any lines at all) and tra-ta-ta!

It compiles ok for two-three-four times, but then it begin to hang while reading this empty UCF. I can't find any workaround for this bug, even closing/opening PlanAhead, removing synth/impl dirs does not help.

Thanks.

[tanders]

The empty top didn't synthsize for me, as the design is empty.

Using this:

module oneFlop (clk, rst, in, out);

   input clk,rst,in;
   output out;

   wire data;
   reg dataIn;

   assign out = dataIn;

   always @(posedge clk)
   begin
      if(rst==1)
      begin
         dataIn <= 1'b0;
      end
      else
      begin
         dataIn <= in;
      end
   end
endmodule

I ran it several times by hand and then via a tcl script that ran synth, opened the design, closed it, repeat for 10 and 20 cycles in the GUI, and saw no issues.

This was on Linux RH5 64bit

[yavv]

Here's example project.

Try to press "Open synthesized design" and PlanAhead will hang at "reading main.ucf" dialog.

[yavv]

Btw, 14.2 hangs too, the issue is not fixed.

[tanders]

It's not hung, it's just slow, in 14.2 at least:

open_run: Time (s): elapsed = 00:04:05 . Memory (MB): peak = 702.445 ; gain = 42.000

on my Linux box it was 2 minutes.

2 minutes on 14.1 on the Linux box as well.

We will look into the slowness, but if you wait couple minutes, it will load for you.

[yavv]

It would be great if Xilinx release the hotfix for this issue.

[sebastian.schopferer]

We have the same problem with PlanAhead 14.1 and 14.2. The long loading time seems not be caused by the ucf-file that is written in the progress window, because it even takes a very long time, when the file is completely empty.

My impression is, that the problem always appears, when I add chipscope cores.

Here is an example:
When I open the synthesized design without chipscope cores it takes 20 seconds:
open_run: Time (s): elapsed = 00:00:22 . Memory (MB): peak = 842.117 ; gain = 27.691

Then I mark 32 nets for debugging with chipscope, use the wizzard to setup the chipscope cores (1 icon, 1 ila, 1 clock domain, 8 signals data+trigger, 24 signals data-only).
After implementation I try to open again the synthesized design , and now it takes almost 7 minutes to open.
open_run: Time (s): elapsed = 00:06:46 . Memory (MB): peak = 1604.414 ; gain = 19.891

When I delete the chipscope cores, opening is fast again.

Is there a fix for this issue available in the meantime?