Design Planning

[stuartdu]

I am using PlanAhead for Partial Reconfiguration. I have made my static design quite large and the dynamic modules very small. It is simply a module with a 4-bit output and constant logic inside. The implementation run-time for the static plus 1 dynamic module is 23 minutes. When I import the static design to my next design run and implement a different dynamic module it still takes 15 minutes. It is my understanding that the second design run simply has to implement the new dynamic module and all the static logic has been imported. I have not included IO Buffers in my dynamic modules. I think I could probably do it by hand in about 2-3 minutes. It only needs to send the logic to the proxy LUTs. Is there any way to know why it is taking so long?

[davidd · Accepted solution]

Stuart,

There's a lot more going on under the hood than just placing and routing your new reconfigurable module here.  The tools need to open and load the imported static design, run a series of checks for Partitions and PR, and then after the new modules are implemented, full design sequences (timing analysis, etc.) are still done.  Yes, there are certainly some areas where this could be improved, especially for a scenario like yours (mostly static, very small RP).  Fortunately, we have a great opportunity for this as we implement this solution in Vivado, and you'll see runtime improvements and more when this flow is released.  PR is scheduled for beta in Vivado later this year.

thanks,

david.