Design Planning

[steview]

We have a design that requires connecting signals to the System Monitor dedicated pins.

How do we do this? I have set them as std_logic types at the top level of my FPGA however PlanAhead says I cannot place I/O on a dedicated pin.

How Do I tell the tools that these are analog inputs that I want to connect up?

[jmcgrath]

As these are the dedicated inputs (VP/VN) - they are always connected, so there is no need to include them in the HDL, or any IO planning.

In the case of the 16 pairs of auxiliary inputs, if you are using them then they only need to be connected to the design's top level in the HDL. You do not need to place them during IO planning, as these inputs have fixed pin locations and so the SW is smart enough to take care of this.

Cheers

John