Sign In

Don't have a Xilinx account yet?

  • Choose to receive important news and product information
  • Gain access to special content
  • Personalize your web experience on Xilinx.com

Create Account

Username

Password

Forgot your password?
XClose Panel
Xilinx Home
Reply
Visitor
siddadd
Posts: 10
Registered: ‎04-03-2012
0
Accepted Solution

Unable to Floorplan

I imported my project from ISE into PlanAhead.

 

After carrying out the HDL flow and generating the bitstream, I am trying to floorplan my design.

 

The problem is none of the modules are showing up in the device tab on the right. Even when I highlight a primitive, I don't see anything. Attaching a screenshot of the same.

 

Is there some issue that can be fixed?

 

Thanks,

 

Siddharth

Xilinx Employee
tanders
Posts: 70
Registered: ‎03-31-2011

Re: Unable to Floorplan

Look at the Implemented Design instead of the Netlist Design if you want to see the current placement.  Only constrained objects will be displayed in Netlist Design.