Hello ,I have a doubt.
I have a problem with a little part of my code when migrate my project from ISE to PinAhead project.
The question is:
Why pinAhead inferred a IDDR with part of vhdl code?
I don't instantiate DDR.
Can I Do something to Avoid It? In ise I don´t has this problem.
the objective of the code is to sample an input signal with frecuency of 27M
through a clock with frecuency of 270 to find the optimum point of sampling.
captured 8 samples per cycle of the input signal.
I can not use IDDR because it would need 4 iDDR in parallel for the same input pin, and this is not posible.
the error shown in pinahead is as follows:
[NgdBuild 604] logical block 'asi_rx_inst/DVBASI_INST1/asi_receiver/dru_8phase/lk[3].QRlk[3].QF' with type 'IDDR' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'IDDR' is not supported in target 'spartan6'.
the code that gives me problems is:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--library UNISIM;
--use UNISIM.VCOMPONENTS.all;
entity DRU is
port(CLK270:in STD_LOGIC_VECTOR(3 downto 0); -- 270MHz 4-phase Clocks (0, 45, 90 and 135 degrees)
SI:in STD_LOGIC; -- 270Mbps Serial Data In
DOUT:out STD_LOGIC_VECTOR(1 downto 0); -- Serial Data Out (0, 1 or 2 bits/clock)
DV:out UNSIGNED(1 downto 0)); -- Number of valid output bits (0, 1 or 2 bits/clock)
end DRU;
architecture TEST of DRU is
signal DATA,DATA1D,DATA2D,DATA3D,DATA4D,cEDGE,EDGE,E:STD_LOGIC_VECTOR(7 downto 0):=(others=>'0');
signal Q:UNSIGNED(2 downto 0):=(others=>'0');
signal DVE:UNSIGNED(DV'range):=(others=>'0');
begin
lk:for K in CLK270'range generate
signal QR,QF,QFD,RQ,FQ:STD_LOGIC:='0';
begin
process(CLK270(K))
begin
if falling_edge(CLK270(K)) then
QF<=SI;
end if;
end process;
process(CLK270(K))
begin
if rising_edge(CLK270(K)) then
QR<=SI;
QFD<=QF;
end if;
end process;
process(CLK270(0))
begin
if rising_edge(CLK270(0)) then
RQ<=QR;
FQ<=QFD;
end if;
end process;
DATA(K)<=FQ;
DATA(K+4)<=RQ;
end generate;
process(CLK270(0))
begin
if rising_edge(CLK270(0)) then
EDGE<=DATA xor DATA(6 downto 0)&DATA1D(7);
E<=EDGE or EDGE(6 downto 0)&EDGE(7) or EDGE(0)&EDGE(7 downto 1);
case Q is
when "000"=>if E(2)='1' then
Q<="111";DVE<="10";
elsif E(6)='1' then
Q<="001";DVE<="01";
else
DVE<="01";
end if;
when "001"=>if E(3)='1' then
Q<="000";DVE<="01";
elsif E(7)='1' then
Q<="010";DVE<="01";
else
DVE<="01";
end if;
when "010"=>if E(4)='1' then
Q<="001";DVE<="01";
elsif E(0)='1' then
Q<="011";DVE<="01";
else
DVE<="01";
end if;
when "011"=>if E(5)='1' then
Q<="010";DVE<="01";
elsif E(1)='1' then
Q<="100";DVE<="01";
else
DVE<="01";
end if;
when "100"=>if E(6)='1' then
Q<="011";DVE<="01";
elsif E(2)='1' then
Q<="101";DVE<="01";
else
DVE<="01";
end if;
when "101"=>if E(7)='1' then
Q<="100";DVE<="01";
elsif E(3)='1' then
Q<="110";DVE<="01";
else
DVE<="01";
end if;
when "110"=>if E(0)='1' then
Q<="101";DVE<="01";
elsif E(4)='1' then
Q<="111";DVE<="01";
else
DVE<="01";
end if;
when "111"=>if E(1)='1' then
Q<="110";DVE<="01";
elsif E(5)='1' then
Q<="000";DVE<="00";
else
DVE<="01";
end if;
when others=>null;
end case;
DATA1D<=DATA;
DATA2D<=DATA1D;
DATA3D<=DATA2D;
DATA4D<=DATA3D;
DOUT<=DATA4D(7)&DATA3D(TO_INTEGER(Q));
DV<=DVE;
end if;
end process;
end TEST;
