Design Planning

[sfor]

Can't assign I/O Ports debug1 and debug2 in PlanAhead 13.4. Just manual in .ucf file.

Can anyone help me?

Thank's

Project attatched.

[sfor]

can't assign debug1 to P60 and debug2 to P63

[tanders]

I downloaded your design and was able to place debug1/2 in P60/63 (had to remove the ports that were occupying those sites).  What error/issue are you seeing specifically, does the site not show up as valid, etc...?

[sfor]

When you close RTL Design and than open it again. pins will be false connected.

Thank you!

[tanders]

This is a known issue that we're looking into.  Please use the Netlist/Synthesized design as a work around for now.

[tanders]

This issue has been resolved in the 14.1 release, which will be available shortly.

[sfor]

Thanks for your time!

[tanders]

You're welcome.

T