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Visitor
puxiangjun1982
Posts: 11
Registered: ‎06-20-2012
0

map and PAR error

未命名.jpg

 

When I use planahead13.4 to compile the virtex-6 project, finished the compile, report the error as above picture,but it's don't halt, the resoult is also normally, why?

Xilinx Employee
tanders
Posts: 70
Registered: ‎03-31-2011
0

Re: map and PAR error

I'm not aware of any known issues regarding this message.

Do you see this message consistently?  If you reset the implementation run and re-implement do you still see it?

 

If either of the above suggestions work:

Can you try this in the latest 14.1 software?

Can you send us the design to reproduce internally?

Visitor
puxiangjun1982
Posts: 11
Registered: ‎06-20-2012
0

Re: map and PAR error

planAhead 14.1 compile result is the same as 13.4 for this error,and i reset and re-implement,too. this error appeared every time.

For reasons of confidentiality of the project, I can not send design to you.sorry!