I am implementing a design on a Xilinx ML605 board using PlanAhead 12.4. The mapper fails with:
PhysDesignRules: 2216 - IDELAYCTRL not found for CLOCKREGION_X1Y2. The IODELAYE1 block system_i/DDR3_SDRAM/...... has an IDELAY_TYPE attribute of FIXED, VARIABLE, or VAR_LOADABLE. This programming requires that there be an IDELAYCTRL block programmed within the same clock region.
And 2 more of the same with different netnames.
I've read that IODELAY blocks require a location constrained IDELAYCTRL to be instantiated, or to use a flat design with 1 single unconstrained IDELAYCTRL that will be shared.
This system compiles fine in ISE 12.4, when I specify system.xmp. In PlanAhead, I have added all the ngc files associated with the system specified in system.xmp. it doesn't seem like I can add system.xmp to planAhead.
I had a similar problem like this with a different design that worked in ISE when "keep hierarchy" was set to no and didn't work the moment I set "keep hierarchy" to yes. I noticed in Planahead that that option in synthesis is gone, i'm assuming because in the planAhead flow you always want to "keep hierarchy"
How do I fix this? DO I somehow need to go into EDK and add IDELAYCTRLs? the system.ngc and various other ngc files are generated by the EDK GUI right? Is there a way to modify one of the vhd wrapper files and manually regenerate the ngc files?
