Sign In

Don't have a Xilinx account yet?

  • Choose to receive important news and product information
  • Gain access to special content
  • Personalize your web experience on Xilinx.com

Create Account

Username

Password

Forgot your password?
XClose Panel
Xilinx Home

Design Planning

Reply
Topic Options
onemanshow
Regular Visitor
onemanshow
Posts: 35
Registered: ‎05-20-2009
0
Accepted Solution

not enough detail on planAhead 11.1 timing report

Options

‎05-23-2009 03:22 PM

I am using planAhead to do post-layout timing analysis. When I import the timing report, violating path doesn't show everything. 

timing report from planAhead showed one path went through few gates, but in ISE timing analyzer report, the same path went through way more gates than what planAhead was showing. I was trying the fix timing based on planAhead report, and effort went nowhere since I didn't know there were many more gates involved. Does anyone know why planAhead does this? Is there some kind of setting I need to do in planAhead to show all detailed path delay?

 

In planAhead 10.1, there was exploreAhead, so I can try the floorplan before running ISE. I don't see that feature anymore in 11.1. Anyone know what happened? Do we need to purchase exploreAhead separately?

  

 

 

 

 

Message 1 of 11 (4,099 Views)
 
Reply
Please use plain text.
 
Xilinx Employee
Xilinx Employee
ywu
Posts: 2,861
Registered: ‎11-28-2007
0

Re: not enough detail on planAhead 11.1 timing report

Options

‎05-26-2009 06:42 AM

onemanshow wrote:

> I am using planAhead to do post-layout timing analysis. When I import the timing report, violating path doesn't show everything. 

> timing report from planAhead showed one path went through few gates, but in ISE timing analyzer report, the same path went through way more gates than what planAhead was showing. I was trying the fix timing based on planAhead report, and effort went nowhere > since I didn't know there were many more gates involved. Does anyone know why planAhead does this? Is there some kind of setting I need to do in planAhead to show all detailed path delay?

 

[Jim] PlanAhead uses the instance/net names from the source netlists (edf and/or ngc). When you implement the design (i.e. run map/par), the backend tools may change/remove some nets/instances due to optimization. The timing report is based on the net/instance names in the final implementated design, which may or may not be the same as in the source netlists. When PlanAhead can't find a match between the source netlists and the timing report, you will see the inconsistency on PlanAhead GUI.

 

 

In planAhead 10.1, there was exploreAhead, so I can try the floorplan before running ISE. I don't see that feature anymore in 11.1. Anyone know what happened? Do we need to purchase exploreAhead separately?

 

[Jim] It's called "Tools->Run Implementation..." now in 11.1

 

Cheers,

Jim

 

  

 

 

 

 

 

Cheers,
Jim
Message 2 of 11 (4,078 Views)
 
Reply
Please use plain text.
 
onemanshow
Regular Visitor
onemanshow
Posts: 35
Registered: ‎05-20-2009
0

Re: not enough detail on planAhead 11.1 timing report

Options

‎05-26-2009 05:42 PM

Hello Jim,

 

Thanks for the info.

So when timing report is imported to planAhead after PAR, it still doesn't know anything about implementation? I was expecting planAhead to import all implementation results, so I can trace routing of critical path. If planAhead can't do that, its not much of timing analysis tool.  

Message 3 of 11 (4,059 Views)
 
Reply
Please use plain text.
 
Xilinx Employee
Xilinx Employee
ywu
Posts: 2,861
Registered: ‎11-28-2007
0

Re: not enough detail on planAhead 11.1 timing report

Options

‎05-27-2009 01:23 PM

It does import all implementation result. Certain instances/nets names will be displayed differently if the names in the implentation result don't match the source netlist. Having said that, the transformation of instance/net names in backend tools (map/par) doesn't dramaticlly change the names, so PlanAhead will be able match the implementation result well with the netlist and can be very use for analyzing timing results.

 

Cheers,

Jim

 

Cheers,
Jim
Message 4 of 11 (4,044 Views)
 
Reply
Please use plain text.
 
onemanshow
Regular Visitor
onemanshow
Posts: 35
Registered: ‎05-20-2009
0

Re: not enough detail on planAhead 11.1 timing report

Options

‎05-27-2009 02:48 PM

Hello Jim,

 

    You are right. Not all the names are the same, but its enough to identify the path. The bigger issue is that planAhead shows different level of logic in critical path. In ISE11.1,  I open up one critical path and I see about 10 level of logic, but the same path in planAhead shows only 5.  This is after implementation is imported to planAhead. I don't know if this is standard behavior. 

Message 5 of 11 (4,040 Views)
 
Reply
Please use plain text.
 
Xilinx Employee
Xilinx Employee
ywu
Posts: 2,861
Registered: ‎11-28-2007
0

Re: not enough detail on planAhead 11.1 timing report

Options

‎05-29-2009 10:13 AM

Without looking at the path in PA (planahead for short) and in the timing report, it's hard to say where this discrepancy come from. Would it be possible to post the path?  What tool options did you use with map?

 

Cheers,

Jim

 

Cheers,
Jim
Message 6 of 11 (4,017 Views)
 
Reply
Please use plain text.
 
onemanshow
Regular Visitor
onemanshow
Posts: 35
Registered: ‎05-20-2009
0

Re: not enough detail on planAhead 11.1 timing report

Options

‎06-02-2009 04:20 PM

here is one example

 

timing report from ISE

 

 Maximum Data Path: dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/dp_rx_inst/DPP_RX_FIFO_INST/rd_ptr_1 to dut_core_inst/usb_inst/link_inst/link_tx_inst/lcrd_q_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X52Y76.BQ      Tcko                  0.396   dp_rx_inst/DPP_RX_FIFO_INST/rd_ptr<3>
                                                       dp_rx_inst/DPP_RX_FIFO_INST/rd_ptr_1
    SLICE_X50Y78.C1      net (fanout=303)      1.189   dp_rx_inst/DPP_RX_FIFO_INST/rd_ptr<1>
    SLICE_X50Y78.C       Tilo                  0.086   dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/dp_rx_inst/DPP_RX_FIFO_INST/COUNT_3_BRB7
                                                       dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/lut5184_40
    SLICE_X53Y77.A2      net (fanout=1)        0.908   dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/lut5184_40
    SLICE_X53Y77.A       Tilo                  0.086   dut_core_inst/R_EPCFG_ENABLE_bus_sync/in_d2<27>
                                                       dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/lut5185_41
    SLICE_X55Y75.C4      net (fanout=11)       0.582   dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/lut5185_41
    SLICE_X55Y75.C       Tilo                  0.086   dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/dp_rx_inst/DPP_RX_FIFO_INST/fifo_reg_array_15_67
                                                       dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/lut5197_169
    SLICE_X55Y80.D4      net (fanout=3)        0.648   dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/lut5197_169
    SLICE_X55Y80.D       Tilo                  0.086   dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/N40
                                                       dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/lut5202_173_SW0
    SLICE_X55Y80.C6      net (fanout=1)        0.119   dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/N40
    SLICE_X55Y80.C       Tilo                  0.086   dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/N40
                                                       dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/lut5202_173
    SLICE_X58Y83.C6      net (fanout=29)       0.497   dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/lut5202_173
    SLICE_X58Y83.C       Tilo                  0.086   dut_core_inst/USB_ED2_WR_GRANT_REPLICA_1073
                                                       dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/dp_rx_inst/RAM_PRI<0>1_F
    SLICE_X58Y83.D5      net (fanout=4)        0.239   dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/dp_rx_inst/N349
    SLICE_X58Y83.D       Tilo                  0.086   dut_core_inst/USB_ED2_WR_GRANT_REPLICA_1073
                                                       dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/dp_rx_inst/RAM_PRI<0>1
    SLICE_X56Y82.A5      net (fanout=22)       0.453   dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/DP_RX_RAM_PRI<0>
    SLICE_X56Y82.A       Tilo                  0.086   dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/lut26896_1027
                                                       dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/lut5273_252
    SLICE_X57Y80.D3      net (fanout=68)       0.686   dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/lut5273_252
    SLICE_X57Y80.D       Tilo                  0.086   dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/dp_rx_inst/data_ED1<48>
                                                       dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/][18316_263
    SLICE_X78Y82.D4      net (fanout=2)        1.080   dut_core_inst/usb_inst/epc_ss_inst/EPC_RX_RAM_WR_BE<2>
    SLICE_X78Y82.D       Tilo                  0.086   dut_core_inst/usb_inst/epc_ss_inst/epc_tx_inst/tp_tx_inst/TP_TX_FIFO_INST/fifo_reg_array_6_23
                                                       dut_core_inst/usb_inst/epc_ss_inst/][16547_6525
    SLICE_X78Y82.C6      net (fanout=1)        0.133   dut_core_inst/usb_inst/USB_SS_RAM_WR_BE<2>
    SLICE_X78Y82.C       Tilo                  0.086   dut_core_inst/usb_inst/epc_ss_inst/epc_tx_inst/tp_tx_inst/TP_TX_FIFO_INST/fifo_reg_array_6_23
                                                       lut204363_28491
    SLICE_X58Y92.C2      net (fanout=12)       1.490   lut204363_28491
    SLICE_X58Y92.C       Tilo                  0.086   dut_core_inst/ram_inst/lut1241_23885
                                                       dut_core_inst/ram_inst/lut1242_23886
    SLICE_X64Y91.A5      net (fanout=47)       0.788   dut_core_inst/ram_inst/lut1242_23886
    SLICE_X64Y91.A       Tilo                  0.086   dut_core_inst/R_EPCFG_STR_EN_U<17>
                                                       dut_core_inst/ram_inst/lut1243_23887
    SLICE_X78Y83.D6      net (fanout=12)       0.770   dut_core_inst/RAMARB2_RD_OK
    SLICE_X78Y83.D       Tilo                  0.086   dut_core_inst/usb_inst/epc_ss_inst/lmp_inst/LMP_RX_RAM_WR_BE<4>_REPLICA_658
                                                       dut_core_inst/usb_inst/epc_ss_inst/lut25454_7336
    SLICE_X64Y75.B6      net (fanout=6)        0.805   dut_core_inst/usb_inst/epc_ss_inst/lut25454_7336
    SLICE_X64Y75.B       Tilo                  0.086   dut_core_inst/usb_inst/epc_ss_inst/epc_rx_inst/tp_rx_inst/data_ED1<37>
                                                       dut_core_inst/usb_inst/epc_ss_inst/RXH_EPC_ADV
    SLICE_X61Y59.B6      net (fanout=1)        0.951   dut_core_inst/usb_inst/epc_ss_inst/RXH_EPC_ADV
    SLICE_X61Y59.B       Tilo                  0.086   USB_DBG_OUT<40>
                                                       dut_core_inst/usb_inst/epc_ss_inst/][16617_6748
    SLICE_X65Y55.C5      net (fanout=3)        0.598   dut_core_inst/usb_inst/RXH_ADV_epc
    SLICE_X65Y55.C       Tilo                  0.086   dut_core_inst/usb_inst/epc_ss_inst/epc_tx_inst/dp_tx_inst/DPP_TX_FIFO_INST/fifo_reg_array_0_19
                                                       ][134806_61987
    SLICE_X64Y55.CE      net (fanout=1)        0.248   ][134806_61987
    SLICE_X64Y55.CLK     Tceck                 0.195   dut_core_inst/usb_inst/link_inst/link_tx_inst/lcrd_q<2>
                                                       dut_core_inst/usb_inst/link_inst/link_tx_inst/lcrd_q_2
    -------------------------------------------------  ---------------------------
    Total                                     14.237ns (2.053ns logic, 12.184ns route)
                                                       (14.4% logic, 85.6% route)

 

Timing report from planAhead

 

 Maximum Data Path: pblock_epc_ss_inst/pblock_epc_rx_inst/epc_rx_inst/dp_rx_inst/DPP_RX_FIFO_INST/rd_ptr_1 to link_inst/link_tx_inst/lcrd_q_2
    Location             Delay type         Delay(ns)  Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X52Y76         FDCE (Tcko)            0.396  pblock_epc_ss_inst/pblock_epc_rx_inst/epc_rx_inst/dp_rx_inst/DPP_RX_FIFO_INST/rd_ptr_1
                          net (fanout=303)                   1.189  pblock_epc_ss_inst/pblock_epc_rx_inst/epc_rx_inst/dp_rx_inst/DPP_RX_FIFO_INST/rd_ptr[1]
    SLICE_X58Y83         LUT6 (Tilo)               3.270  pblock_epc_ss_inst/pblock_epc_rx_inst/epc_rx_inst/dp_rx_inst/RAM_PRI<0>1_F
                                      net (fanout=4)         0.239  pblock_epc_ss_inst/pblock_epc_rx_inst/epc_rx_inst/dp_rx_inst/N349
    SLICE_X58Y83         MUXF7 (Tilo)           0.086  pblock_epc_ss_inst/pblock_epc_rx_inst/epc_rx_inst/dp_rx_inst/RAM_PRI<0>1
                                     net (fanout=22)        0.453  pblock_epc_ss_inst/pblock_epc_rx_inst/epc_rx_inst/DP_RX_RAM_PRI[0]
                                      net (fanout=2)         1.938  EPC_RX_RAM_WR_BE[2]
                                       LUT6                   0.000  pblock_epc_ss_inst/RAM_WR_BE<2>1
                                      net (fanout=1)         0.219  USB_SS_RAM_WR_BE[2]
                                      net (fanout=12)        3.306  RAMARB2_RD_OK
                                      logic (Tilo)           0.977  RXH_EPC_ADV
                                      net (fanout=1)         0.951  RXH_EPC_ADV
                                      LUT2                   0.000  pblock_epc_ss_inst/RXH_ADV1
                                      net (fanout=3)         0.684  RXH_ADV_epc
    SLICE_X64Y55         FDCE (Tceck)           0.529  link_inst/link_tx_inst/lcrd_q_2
    -------------------------------------------------  ---------------------------
    Total                                      14.237ns

 

  planAhead report looks like a summary instead of detailed analysis.  PlanAhead report is generated when I did ISE Tools --> PlanAhead --> Analyze Timing. 

Also when I open planAhead through ISE, I don't see run implementation option anywhere. However if I open PlanAhead as stand alone, I see run Implementation option. Why is there feature difference?

 

Thanks

 

Message 7 of 11 (3,981 Views)
 
Reply
Please use plain text.
 
Xilinx Employee
Xilinx Employee
ywu
Posts: 2,861
Registered: ‎11-28-2007
0

Re: not enough detail on planAhead 11.1 timing report

Options

‎06-03-2009 07:37 AM

Looks like you turned on global optimization and retiming options in map as some of the signal names have the BRB suffix, which usually means map did register balancing on these paths. When that happes, these paths will be different (signal names as well as logic levels) from the original netlist.

 

I would first find out the critical paths in a design as it is written (i.e. no retiming or register balancing) and see if anything can be done in the source code to improve the timing. 

 

Cheers,

Jim

 

 

 

Cheers,
Jim
Message 8 of 11 (3,972 Views)
 
Reply
Please use plain text.
 
onemanshow
Regular Visitor
onemanshow
Posts: 35
Registered: ‎05-20-2009
0

Re: not enough detail on planAhead 11.1 timing report

Options

‎06-03-2009 10:17 AM

Hello Jim,

 

     We need to use global optimization to meet timing. If planAhead can't display all the optimization PAR did, then it is not useful as timing analysis tool. What I want to see is exact routing after PAR. What can I use to see this? With ISE 10.1, I can double click on a path and it will open up floorplanner and it shows exact routing. With ISE11.1, I don't see this feature. 

 

Thanks

 

Message 9 of 11 (3,965 Views)
 
Reply
Please use plain text.
 
Xilinx Employee
Xilinx Employee
ywu
Posts: 2,861
Registered: ‎11-28-2007
0

Re: not enough detail on planAhead 11.1 timing report

Options

‎06-05-2009 10:42 AM

You need to keep your ultimate goal in mind: closing timing on your design. If the timing report shows that your critical paths are the ones optimized by the implementation tools, even if you had the best analysis tool, you can't do anything about them to achieve your goal (again closing timing). Those paths don't exist in your source code nor in your netlist, so you can't modify source code to address the issues nor can you constraint them in UCF. This is why I suggest you find out the real critical paths are in your design and handle them accordingly.

 

Cheers,

Jim

Cheers,
Jim
Message 10 of 11 (3,938 Views)
 
Reply
Please use plain text.