Design Planning

[asim2010]

I have sp601 board(spartan 6 -csg324 -2)

I m new to fpga design.

when i assign pins in planahead some of the pins has red marking on the slew and output drive for a IOSTANDARD.

I m assuming that means that the right slew rate and output drive is not specified for IOSTANDARD. Is the assumption right?

Also , I would like to know how to choose IOSTANDARD for a pin and also slew rate and output drive for the pin.

The planahead redmarking are shown  in the attached file.

I would really appreciate if some one can help me out.

[gszakacs]

You have to watch out for some newer FPGA families.  It turns out that in the lower cost

devices like Spartan, one way they reduce the IOB area is to limit the functionality on

a bank by bank basis.  So you can have one bank that allows LVDS I/O with termination

but not high drive on LVCMOS, and another that allows high drive on LVCMOS but no

LVDS output and no termination on LVDS input.  Take a close look at the datasheet

for your part and make sure the IOSTANDARD for the bank you chose allows the

drive strength you need.

Regards,

Gabor