04-07-2012 01:45 PM
I have design and implemented a very simple design, and now I would like to get some information on power consumption. So, place and route was OK. Then i have generated the primetime netlist model and run post route simulation with checked option to generate SAIF file. After generating SAIF file, i run Xpower Analyzer, but the problem is, three identical blocks have zero power consumption. THose three block are clocked from internaly generated clock signal, which is manualy buffered using BUFG cell. I have attached detailed report from Xpower.
Hope somebody can help me.
04-08-2012 09:07 AM
It has no idea what the clock frequency is. So, with no clock, there is only static power, whuch varies hardly is all ragardless of the design.
Xilinx San Jose
04-08-2012 09:45 AM
Ok, but how to specify that I have another clock. In Xpower tool, I am able to see that I have two clock domains, it is also showing me the frequency. I don't know if u have looked in my .pwr file attached to he previous message, i have clk signal and lfsr_clk. Lfsr is derived from clk using simple prescaler. Clk has fanout of 3 and lfsr clk has roughly 48, and tool says clk signal consumes more power.
04-09-2012 07:05 AM
Also, your design is so small, that I doubt there is much difference between nothing in the device, and your design (<4%).
Xilinx San Jose
04-09-2012 09:02 AM
OK, I understand. I just want to be clear about something. Is it enough to make some clock signal from logic and manualy insert buffer or I should somehow tell the tool that generated signal is used for clocking. If the last is correct, any suggestions?
Thank you very much