Design Tools - Others

[tloesch]

I am trying to debug a project for SP605 board. I am using ISE 11.5. I have instantiated an ICON and ILA cores, but when I try to debug all I receive is waiting on core to be armed. I have received a similar message in the past that included the text slow or stopped clock. In that case the clock I was using was not working. I have successfully used ChipScope on this project and sometimes it works as expected but in the last week all I seem to get is the message waiting on core to be armed. I know that the main clock is working based on LED and serial output. Below is the instantiation: wire [35:0] CONTROL0; wire [10:0] TRIG0; wire [3:0] TRIG1; wire [31:0] TRIG2; wire [2:0] TRIG3; wire [7:0] TRIG4; wire [5:0] TRIG5; chipscope_icon Icon_debugger ( .CONTROL0(CONTROL0) // INOUT BUS [35:0] ); chipscope_ila ILA_debugger ( .CONTROL(CONTROL0), // INOUT BUS [35:0] .CLK(ECLK), // IN .TRIG0(TRIG0), // IN BUS [10:0] .TRIG1(TRIG1), // IN BUS [3:0] .TRIG2(TRIG2), // IN BUS [31:0] .TRIG3(TRIG3), // IN BUS [2:0] .TRIG4(TRIG4), // IN BUS [7:0] .TRIG5(TRIG5) // IN BUS [5:0] ); assign TRIG0 = {Place,Owner, New_Position}; assign TRIG1 = Level; assign TRIG2 = Loc; assign TRIG3 = Place; assign TRIG4 = State; assign TRIG5 = Position; During MAP I receive a large number of messages that parts of ILA is being removed due to loadless block or sourceless single. Is that normal? Any help you can provide would be appreciated.

[tloesch]

Attempt to clean up the formatting

wire [35:0] CONTROL0;

 wire [10:0] TRIG0;

 wire [3:0] TRIG1;

 wire [31:0] TRIG2;

wire [2:0] TRIG3;

wire [7:0] TRIG4;

wire [5:0] TRIG5;

 chipscope_icon Icon_debugger (

 .CONTROL0(CONTROL0) // INOUT BUS [35:0]

 );

chipscope_ila ILA_debugger (

 .CONTROL(CONTROL0), // INOUT BUS [35:0]

 .CLK(ECLK), // IN

 .TRIG0(TRIG0), // IN BUS [10:0]

 .TRIG1(TRIG1), // IN BUS [3:0]

 .TRIG2(TRIG2), // IN BUS [31:0]

 .TRIG3(TRIG3), // IN BUS [2:0]

 .TRIG4(TRIG4), // IN BUS [7:0]

 .TRIG5(TRIG5) // IN BUS [5:0]

 );

assign TRIG0 = {Place,Owner, New_Position};

assign TRIG1 = Level;

assign TRIG2 = Loc;

assign TRIG3 = Place;

assign TRIG4 = State;

assign TRIG5 = Position;

[joelby]

---

During MAP I receive a large number of messages that parts of ILA is being removed due to loadless block or sourceless single. Is that normal?

---

No, if your ILA logic is being removed, something is wrong. There could be a typo - I recommend using `default_nettype none so that typos involving incorrect signal names generate errors. Examining all of the warnings carefully should help you to find the problem.

[gszakacs]

Also make sure that the nets you are scoping are not being trimmed.  If you have nets that go nowhere but the

ILA, then you need to place a KEEP attribute on those nets to avoid trimming.  The ILA is not treated as a load

on a signal in the traditional sense of something that eventually affects an output pad of the FPGA.

-- Gabor

[tloesch]

Thanks for the quick reply.  I added `default_nettype none at the top of the modules but it only identified a single issue in a different module than the debugger.  Below is a list of some of the output messages from MAP.  It is even removing the majority of the CONTROL0 signals which is the control between ICON and ILA.

"ILA_debugger/U0/I_NO_D.U_ILA/U_STAT/U_DSR" (ROM)

removed.

Loadless block

"Icon_debugger/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_

LUT" (ROM) removed.

Loadless block

"Icon_debugger/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_

LUT" (ROM) removed.

Loadless block

"Icon_debugger/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_

LUT" (ROM) removed.

Loadless block

"Icon_debugger/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_

LUT" (ROM) removed.

Loadless block

"Icon_debugger/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_

LUT" (ROM) removed.

Loadless block

"Icon_debugger/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_L

UT" (ROM) removed.

Loadless block

"Icon_debugger/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_L

UT" (ROM) removed.

Loadless block

"Icon_debugger/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_L

UT" (ROM) removed.

Loadless block

"Icon_debugger/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_L

UT" (ROM) removed.

Loadless block

"Icon_debugger/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_L

UT" (ROM) removed.

Loadless block

"Icon_debugger/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_L

UT" (ROM) removed.

Loadless block

"Icon_debugger/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_L

UT" (ROM) removed.

Loadless block

"Icon_debugger/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_L

UT" (ROM) removed.

Loadless block

"Icon_debugger/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_L

UT" (ROM) removed.

The signal "CONTROL0<10>" is sourceless and has been

removed.

The signal "CONTROL0<11>" is sourceless and has been

removed.

The signal "CONTROL0<15>" is sourceless and has been

removed.

 Sourceless block

"ILA_debugger/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_

MUX2/Mmux_O1567" (ROM) removed.

  The signal

"ILA_debugger/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_

MUX2/Mmux_O1567" is sourceless and has been removed.

The signal "CONTROL0<16>" is sourceless and has been

removed.

The signal "CONTROL0<17>" is sourceless and has been

removed.

The signal "CONTROL0<18>" is sourceless and has been

removed.

The signal "CONTROL0<19>" is sourceless and has been

removed.

[joelby]

I vaguely recall that the most informative messages about unconnected nets might come from synthesis - but you should really read and think about every single warning.

I don't think I've had problems with ILA-only connections being trimmed when instantiating ILA directly rather than using the ChipScope core inserter, but you could try KEEP attributes. Perhaps you could put the complete output from everything up at pastebin.com or similar for us to look at?