05-02-2012 06:26 AM
There was a chipscope problem with 13.2 AFAIR when exceeding 2048 samples which was considered to be solved in 13.3,
Now I again have something like that:
A simple Design @40MHz compiles and runs with with a ChipScopeProject with some 40 signals and 8192 samples. Altogerher 7% of the BRAMs are used.
Increasing to 16384 causes MAP to fail, the same problem occurs when I try to fit 80 signals with 8192 samples.
Error message is:
Place:543 - This design does not fit into the number of slices available in this device due to the complexity of the design and/or constraints.
Unplaced instances by type:
BLOCKRAM 21 (45.7)
Please evaluate the following:
- If there are user-defined constraints or area groups:
Please look at the "User-defined constraints" section below to determine
what constraints might be impacting the fitting of this design.
Evaluate if they can be moved, removed or resized to allow for fitting.
Verify that they do not overlap or conflict with clock region restrictions.
See the clock region reports in the MAP log file (*map) for more details
on clock region usage.
Anybody has an idea, what could be the reason?
There are no area constraints, just a timing constraint on the input osc
There is only one MCM used, offering 40 MHz for both design clock and chipsscope clock
The Design goal was changed from "balanced" to "area" whith no effect.
05-02-2012 07:26 AM
It's likely that ChipScope is constraining the block RAMs into area groups or RLOC's
and that is causing it to fail placement even though it doesn't use up all of the block RAM. I seem
to remember that ChipScope likes all its BRAMs in a single column.
So the error message is probably due to ChipScope and not your design settings. You might
want to see if you can set Map to ignore RLOC constraints. That might get you past the error.
05-02-2012 07:54 AM
Hm, at the moment the design does not map at all, even without any chipscope def file. It seems to be catched somehow makeing use of old files I assume.
I already cleaned the project twice with no effect.
It says "Unusually high hold time violation detected among 153 connections. " which does not make any sense and did not occur so far.
(I did not change any source code from yesterday, just am exploring the design with different signals)
05-04-2012 08:51 AM
This Project is somehow ruined and I cannot find out, why. No matter, what I do it does not map are meets timing.
I built a new project with the same sources and it worked again.
But now the same problem: more than 8192 samples are not possible.
I did as recommended above, and set the "use RLOC contrainst to "NO" " but it does not work either.
07-02-2012 05:13 AM
did so, and it seems this might be a problem of migrating projects from 13.x to 14.1.
When using only 14.1 with a fresh project and a new fresh chip scop definition, it seems to work.
Will check this soon for larger designs.