Design Tools - Others

[prdorrell]

Hello all,

I'm using Chipscope 11.4 to analyse PCIe packets in a reference design. To trigger on either the trn_rsof (receive start of frame) or trn_tsof (transmit start of frame) would seem easy enough using two match units (M0 or M2). Unfortunately many of the received packets are broadcast messages sent by the Root Complex ... and I want to filter these out using a third match unit (M1). So, ideally,  what I want is:

(M0 && !M1) || M2

However, Chipscope allows me to set a logic equation using && (AND) or || (OR) ... but not both!

Does anyone have any suggestion?

Paul

[jheslip]

Hey Paul, this is not possible you can only use all AND or Ors not a mixture of both. I will file an enhancement CR to request that the developers add this feature.

[scollinson]

Hey there,
Am having the exact same issue as Paul. Is there anyway around this?
This seems like such a simple feature to add and am very surprised no one has asked about it before.
Sam

[eteam00]

1.  Very old thread.  We call this...  a ZOMBIE thread.  Back from the dead!

2.  The obvious workaround is to create the trigger condition as part of your design (yes, it requires a re-compile).  It can be as complex as you need or desire.

-- Bob Elkind

[scollinson]

Hi Bob,

Sorry for digging up the thread, but is that not better than posting another thread with the exact same topic and content?

I have created a wire as below (should this be a reg? I'm new to Verilog) within my design to signal a broadcast packet. Sadly compile time is quite large so this can become quite an annoyance if one needs to change the trigger.

(*keep = "true"*) wire          rp_broadcast = (trn_rd[62:56] == 7'b1110011) ? 1'b1 : 1'b0;

 Thanks,

Sam

[eteam00]

I have created a wire as below (should this be a reg?

I honestly don't know.  I've never had a chipscope license (I'd like to have one, but it's not in my budget).  While you are waiting for a more informed reply, why not give it a try and see if it works.

-- Bob Elkind

[scollinson]

Thanks Bob,

It would seem that it needs to be a register as I cannot find the wire in ChipScope after the ngc is generated.

Sam

[joelby]

If the wire isn't used anywhere, it'll get optimised out, even with a keep constraint. There *may* be some way to stop this from happening, but I haven't found it. I've had the same issue when assigning things to registers as well - as a scummy workaround, you can assign the registers you want to keep out to spare pins.

If you want to stick to using a wire, one way is to generate the ChipScope Pro ILA/ICON cores and instantiate them in code. You can connect any signals you like to the ILA using this method, though you lose the flexibility of being able to monitor registers anywhere in the code hierarchy. On the whole I find it a bit nicer, as long as you don't mind adding debug ports to all of your modules.

[eteam00]

The 'works-every-time' workaround for keeping a net is to bring it to an otherwise unused package pin.

In every FPGA board design, it is a good practice to set aside 6-12 otherwise unused pins as a 'debug' or 'probe' port, and connect these pins to a 'header' where they can be easily probed or jumpered.  Even if you don't have the package pin connected on the board, making the signal an output from your design will ensure that it isn't trimmed.

-- Bob Elkind

[scollinson]

The wire was trimmed with the code above but I was able to keep the register with the following code:

	(*keep = "true"*) reg rp_broadcast;
	always @ (trn_rd) begin
		if (trn_rd[62:56] == 7'b1110011) begin
			rp_broadcast <= 1'b1;
		end else begin
			rp_broadcast <= 1'b0;
		end
	end