Design Tools - Others

[jlqsczw_2007]

As we know, ila core can only accept one clock as the input.

If we want to use chipscope to watch signals of different clock domains in one design file,

what can we do ???

Can we instantiate two ila cores in one design file?

If so,  who knows which one will be triggered?

[mcgett]

If you want to monitor signals from different clock domains then you need to add an ILA core for each domain.  Each one will operate independently from the other.

[rcingham]

If one of the clock domains is much slower than the other, you could use just the fast clock. Note that this will sample the slow domain signals, and any skew may cause some apparently odd effects.

[jlqsczw_2007]

If one of the clock domains is much slower than the other, you could use just the fast clock. Note that this will sample the slow domain signals, and any skew may cause some apparently odd effects.

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 Then I have another question.

How to watch signals of the outputs of combinational circuits with ila core,

especially when the delay of the combinational circuits is unneglectable ,

the sampled signal may not be the ture value due to delay.

As you said ,I can only see the odd effects at that time.

[rcingham]

Not sure if I quite understand what you are trying to acheive, but you won't be able to see combinational glitches from either clock domain in ChipScope, because it samples its inputs.

Suggestion: describe your problem fully.