07-09-2012 02:59 AM
I would like to ask a question about ISE 12.3 Xpower Analyzer. I need to check power consumption of individual blocks in the hierarcy of my design.
I synthesize the design and implement (Translate, Map, Place&Route) it in ISE 12.3 Project Navigator for Spartan 6 device. The design has certain hierarchy in the ISE 12.3 Project Navigator. When I turn on XPower Analyzer after the design is implemented to check the power consumption of individual blocks in the hierarchy (XPower Analyzer > Views > Details > By Hierarchy), part on the hierarchy is missing. I do not understand why? I would expect the hierarchy to be the same as in the Project Navigator. Can anybody explain what might be wrong here?
07-09-2012 11:31 AM
Typically, a design is flattened (hierarchy is removed) when implemented, if you wish to retain hierarchy, you need to direct the synthesis not to flatten the design. When hierarchy is retained, it may use more resources, and it may have trouble meeting timing (because it uses more resources).
Power estimation at the module level is pretty useless, genreally. In a FPGA device, static power is probably dominant, and is always there (can not be turned off). Dynamic power is related to switching activity (toggling) and estimates of this toggling get terribly inaccurate at the module level (probably OK for the entire design, but useless at the module level).
Why do you care?
Xilinx San Jose