Design Tools - Others

[fgalloway04]

I am using the xilinx webpack 9.1 service pack 3 and modelsim xe starter kit to simulate designs. i have downloaded the lastest modelsim Xe libraries from the xilinx website and extracted them into the xilinx directory in the modelsim xe folder.

I have used the 'single port block memory v6.2' xilinx ip core to create a block ram in my project. i have also downloaded the block ram example on the xilinx website. In both cases i get the following warning from modelsim xe:

** Warning: (vsim-3473) Component instance "<instance name>" is not bound.

It adds the signals to the wave and follows the inputs (adds all changes to the waveform viewer etc) but it does not simulate the outputs. It just shows them as unconnected. i know that for the higher end modelsim's you are ment to compile the simulation libraries with  complxlib, but you are not ment to do this for modelsim xe as the libraries are precompiled.

[unicorn70]

Here's a similar error.

http://forums.xilinx.com/xlnx/board/message?board.id=OTHER&message.id=53

Complete the fdo file with the blockram simulation model name

[fgalloway04]

I have tried the command on the link provided for blkmemsp_v6.2.vhd, but i cant get it to work. I am not familiar with the modelsim command syntax so it think i an doing something wrong. I ran the following do file:

do {tbw.fdo}

then tried to run the vcom/clog command after i had done this. Is this the correct way to go about this?

 I also noticed in the post, that the command involved 'vlog' which is the verilog compiler. i am using VHDL, so i assume i should use the 'vcom' command instead (although it doesnt like  '+acc'). I tried the following ( plus a few other things) but i cant get it working. heres what i tried:

vcom  +acc " C:\Modeltech_xe_starter\xilinx\vhdl\src\xilinxcorelib\blkmemsp_v6.2.vhd"

and i get this error:

# ** Error: (vcom-1902) Option "+acc" is either unknown, requires an argument, or was given with a bad argument.

also tried this:
vcom {C:\Modeltech_xe_starter\xilinx\vhdl\src\XilinxCoreLib\blkmemsp_v6.2.vhd}
and got:
# ** Error: (vcom-7) Failed to open design unit file "C:\Modeltech_xe_starter\xilinx\vhdl\src\XilinxCoreLib\blkmemsp_v6.2.vhd" in read mode.

any help you could give me with the syntax would be appreciated.

thanks


Message Edited by fgalloway04 on 10-31-2007 06:41 AM

[unicorn70]

You need to copy this command line to the fdo file.

[kimslot]

hi, anyone found the answer to this problem .. i have the same problem and have worked hours to find out whats wrong .. anyone can help and write what to do?

[krbergh]

Hello.

Once I had the same error with a generated component. It turned out that I had just included a different entity than the one I included in the library. Simple typo-mistake. The compomonent apparently got accepted as a "black box" with uninitialized outputs.

-krbergh

[cevikbas]

  Hello,

  I had the same problem. After long trials I found a work around.

  Try removing the core in the implementation tab; then simulate either with or without adding the same core (".xco" file).

  Another solution is to create a new project.

  Hope this helps,

[walter.baeck@agfa.com]

In my situation, the core was instanciated in a design module by hand, and the testbench around that design module was also written by hand.

After numerous attempts, the core still kept getting represented as a blackbox by ModelSim 6.4b .

Within the design module, the core was declared as a component, and that component was then instanciated.

In the ModelSim "Library" overview, the core was also clearly available in compiled form.

I didn't want to go through the hassle of using a configuration.

After pondering it thoroughly, I solved my problem by declaring the library that the core belonged to.

It's funny, because I was lazily using the same VHDL library to compile everything into :

cores, design modules, testbenches. I would always use -work <MyLib> on ModelSim invokation.

And yet, even while this library MyLib should be known as the work library everywhere,

I still found improvement in this blackbox problem by simply mentioning

     library <MyLib>;

in my design module, where this core was instanciated as a component.

[heber.green]

I had a similar problem when I was trying to implement several modules that contained Xilinx primitives in a 'for generate' statement.

I had something like (where slow_to_fast_sync contained some primitives):

--

INT        : IN STD_LOGIC_VECTOR(31 downto 0);

signal int_sync            : std_logic_vector(31 downto 0);

in_sync : for i in 0 to 31 generate
sync : slow_to_fast_sync port map (INT(i), CLK, int_sync(i)); 
end generate;

--

the int_sync would not be initialized in modelsim and I would get the "not bound" warning.

Just for kicks I modified my code to hard code one of the module instantiations so I had

--

sync0 : slow_to_fast_sync port map (INT(0), CLK, int_sync(0)); 

in_sync : for i in 1 to 31 generate
sync : slow_to_fast_sync port map (INT(i), CLK, int_sync(i)); 
end generate;

--

I kid you not when I say modelsim suddenly stoped giving me the warning and all 32 signals behaved as I expected, even after I returned to my original code. If you're using a for generate statement maybe it is worth a try.

[riemerg]

reviving a topic from the past, but I ran in the same error without any solution to be found.

after fiddling around, this is what did the trick for me:

- in library tab: double-click on the component which is "not bound" to simulate it
- add signals to wave, run simulation
- then switch back to testbench you want to simulate by doubleclicking it
- is solved now