Design Tools - Others

[derbaur]

Hey,

I try to develop a setup (virtex5 fx) which offers the opportunity to update different bitstreams stored in an external BPI-flash over the on board "hard block"PPC (ethernet).

I use the xilflashlib 1.02 to read/write to the external 28F128P30 flash (16MB). 

My memory map of the flash device:

0x000000: bitfile1         (written with Xilinx iMPACT 11)

0x200000: bitfile2         (written with Xilinx iMPACT 11)

0x400000: filesystem  (written with SDK)

0x600000: s-record for the PPC (written with SDK)

On bootup the V5 loads the bitfile1 (with PPC bootloader) and load the srec into RAM. Now I can switch to manually switch to the bitfile2 with the appropriate HWICAP commands.

The problem is that if I read out the flash memory (with PPC) and display the memory content, it works well for the file system and srec memory section- but for the both bitfile sections I read false data content. 

When I perform a complete flash readout (with Xilinx iMPACT 11) I see the correct data.

Have someone an idea??

Thank you!

felix

[gregmeredith]

it sounds like there is some sort of file translation that is going on.  Try to find the sync word and then see if the bits are swapped or if the data is all being translated to ASCII.  AA99 might show up like 5599 if the bits are swapped, or 9955 if there is x16 bit swapping.  If there is an ASCII translation it might looks like 27274545 or something like that.  If there is file manipulation required it might be easy to invert the incomming bus bus[15] = temp [0], bus [14] = temp [1].... to get the data to look right.