Design Tools - Others

[zubin_kumar31]

Hi,

I had a question reg. chipscope storage qualifier. 

The FPGA clock, which i use as the chipscope clock, is 200 MHz. I set chipscope to collect 1024 samples. I have a data_valid signal on which i want to collect the data sample and see it on chipscope. 

The problem is that the data_valid signal takes a lot of time to transition from low to high to indicate a valid data ... like 400 microsec. and so when i run my chipscope, i just see 1 sample. 

i wanted to know if there is a way of using the 200 MHz FPGA clock and have some setting for the storage qualifier that would help in catching 1024 samples ONLY when the data_valid is high. 

currently when i use the storage qualifier setting, i put the data_valid as the and condition ... so any change that i can make here ?

thanks,

Z.

[gszakacs]

I'm having a hard time understanding your problem, but here's a simple explanation

of the storage qualifier:

Chipscope normally stores samples in a buffer all the time on every clock cycle.

When you have a storage qualifier, ChipScope will only store samples on clock cycles

in which the storage qualifier is true.

If you look at the storage qualifier signal as data, it will therefore always appear true,

because any cycle where it wasn't true is not in the buffer.

The storage qualifier is independent of the trigger, and the trigger event will cause

the storage to stop even if the trigger happens on a cycle where the storage qualifier

is not true.  If you only want to trigger on qualified cycles, then you need to AND the

qualifier in the trigger condition.

Reasonable use of the storage qualifier generally requires at least two match units

so you can have independant sources of storage qualification and trigger.  You can

have multiple match units that all use the same trigger word.

The storage qualifier can be a function of any one or more match units.  So can the

trigger.  There is no requirement for the same match unit to be used for both trigger

and storage qualifier, but if you only want to trigger on qualified storage cycles then

you would need to have the same match unit in both, or have more than one match

unit dependent on the same input pattern.

Perhaps this clarifies it somewhat?

-- Gabor

[zubin_kumar31]

hi gabor, 

thanks for your reply. i guess the point you mentioned that interested me is this - When you have a storage qualifier, ChipScope will only store samples on clock cycles in which the storage qualifier is true.

So just to clarify, if i set the chipscope to collect 1024 samples on every rising edge of the clock (which is 200 MHz) and the storage qualifier is a data_valid signal that comes after every 1us, and stays high for just 1 sample or 1 clk cycle, so I should see 1 sample collected, every 1 us in the chipscope, i.e. 1024 samples collected over 1024 usec, even though the 200 MHz clock runs much faster ... so now .. we have collected 1024 samples on every point when the storage qualifier is true and NOT on evey rising edge of the clock ... 

is my interpretation correct?

[gszakacs]

---

zubin_kumar31 wrote:

hi gabor, 

thanks for your reply. i guess the point you mentioned that interested me is this - When you have a storage qualifier, ChipScope will only store samples on clock cycles in which the storage qualifier is true.

So just to clarify, if i set the chipscope to collect 1024 samples on every rising edge of the clock (which is 200 MHz) and the storage qualifier is a data_valid signal that comes after every 1us, and stays high for just 1 sample or 1 clk cycle, so I should see 1 sample collected, every 1 us in the chipscope, i.e. 1024 samples collected over 1024 usec, even though the 200 MHz clock runs much faster ... so now .. we have collected 1024 samples on every point when the storage qualifier is true and NOT on evey rising edge of the clock ... 

is my interpretation correct?

---

Yes.  This is correct.

-- Gabor