Design Tools - Others

[akanksha112]

Hi All,

I have an 8 bit local signal which is used for some internal logic. Now the problem I am facing is when I am debugging using chipscope in the netlist signals , the 5th bit of the signal is trimmed and there is no warning or info regarding this.

I am sharing with you the pice of code related to this . I would be grateful if anyone of you could tell me any hint as to why this could happen. Earlier it was not giving any problem. It is a critical signal and I need to probe on it for my design so cant let go off it .

Here is the part of the code , THE SIGNAL IN QUESTION IS  O_BYTE

PROCESS(CLOCK,RESET)

BEGIN

IF CLOCK'EVENT AND CLOCK = '1' THEN

  IF RESET = '1' THEN

    F_E <= '0' AFTER 1 NS;

     F_D <= '0' AFTER 1 NS;

  ELSIF ((B_SIZE = TRANS_LEN) OR (FLAG_S = '1')) THEN

     F_E <= '0' AFTER 1 NS;

  ELSIF ((B_SIZE_2 = TRANS_LEN) OR (FLAG_S = '1')) THEN

    F_D <= '0' AFTER 1 NS;

 ELSIF ((O_BYTE = X"0A") OR (O_BYTE = X"2A"))THEN

     F_E <= '1' AFTER 1 NS;

 ELSIF ((O_BYTE = X"28") OR (O_BYTE = X"08"))THEN

    F_D <= '1' AFTER 1 NS;

 END IF;

END IF;

END PROCESS;

please reply asap ..

akanksha

[rcingham]

You need to assign a 'keep' attribute to your signal in the VHDL architecture. This is weel documented in the Fine Constrants Guide.

BTW, if you are intending your RESET to be synchronous, it should not be in the process senstivity list.

[juergenatduerr]

You also might uncheck "Trim Unconnected Signals" in MAP's properties

[akanksha112]

Hi Frnds

Well i put the keep attribute for teh signal i wished to probe on the chipscope. However , now I am getting this error. Could someone tell me about it , the reason and the solution for it. I do not wish to modify the exisying design by making any changes in the constyraints too as i want these signals for pure dubugging purpose.

Big block initial random placer cannot find solution. This is due to design being overconstrained by
   user specified or clock region constraints. Try locking down the big blocks to improve this condition.

Please reply as soon as possible

akanksha

[juergenatduerr]

Can you setup a simple / nearly empty design and reproduce the error?