I dont' know if this is a bug that was introduced with 13.4 or not, but I migrated an old project to 13.4 and everything seemed to be OK, until the prompt that asks if I wanted to generate (regenerate) the coregen modules in my design.
So, obviously, I clicked YES and after a few seconds, a cryptic coregen error in ISE would halt the process:
Started : "Regenerate Core".
INFO:sim:172 - Generating IP...
Applying current project options...
Finished applying current project options.
Resolving generic values...
Finished resolving generic values.
Generating IP...
WARNING:sim:89 - A core named <[redacted]_FIFO> already exists in the output
directory. Output products for this core may be overwritten.
ERROR:coreutil - Exception caught when running synthesis!
ERROR:coreutil - Failure to generate output products
ERROR:coreutil:576 - An error occurred while running Java. Please examine the
console or coregen log file for a specific IP related error.
For more information please search the Xilinx Answers Database for this
error: http://www.xilinx.com/support
ERROR:coreutil - XST has returned an error:
ERROR:sim - Error found during generation.
ERROR:sim - Failed to generate '[redacted]_FIFO'. XST has returned an error:
Wrote CGP file for project '[redacted]_FIFO'.
Core Generator regen command failed.
Process "Regenerate Core" failed
OK fine, so I go read coregen.log, located in the same directory where the .xco file is and it's the exact same text as above. That's no help.
Next, I launch the Xilnx CORE Generator stand-alone (as adminsitrator, otherwise it doesn't launch). But I can't load .xco files into that, so I look at the ISE log and I see that in the process of regenerating the core, it created a .cgp, cool! So I load that with CORE Generator. Then I click "Upgrade and regenerate all project IP".
After a few seconds I get the following error window ...notice the console/log in coregen, BINGO!
The error in the console reads:
ERROR:sim - No write access in C:\TEMP\ ERROR:sim - Failed executing Tcl generator.
Well.. let's go look at the my C: drive. Yup, that folder doesn't exist! So I create it, go back to ISE, try to Implement the design again and voila! It works!
Apparently the Xilinx ISE devs decided that hard-coding "C:\TEMP" would be just fine... aaaaaaand, if the folder didn't exist, why create it, or heck, why even notify the user, right?!
tl;dr: Create the folder "C:\TEMP" and carry on.
Anyway, I hope this helps other people with the same issue. Good luck!
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More details:
The ISE project has a couple of coregen FIFOs.
The coregen sources in the design are .xco files.
I'm running Windows 7 64-bit (16GB RAM)
I have to run ISE as adminsitrator (..another bug?), otherwise it wont' run.
