Design Tools - Others

[volatile]

I am trying to use chipscope to test the memory controller using MIG for DDR2 for ML505. I have followed the steps (which are apparently not all correct) given on the below link.

http://www.xilinx.com/products/boards/ml505/ml505_12.1/mig.htm

The chipscope (icon and ila) cores given with the reference design give the following error

ERROR:Xst:1617 - Processing TIMESPEC TS_J_TO_D: user TIMEGRP 'D_CLK' must be previously defined in FROM/TO constraint.
ERROR:Xst:1489 - Constraint annotation failed.

So I tried to generated new cores since the solution on this http://www.xilinx.com/support/answers/32425.htm mentions that the issue has been resolved in 11.1 version and I am using 11.4 version.

Can you tell me the constraints I might have to add in .ucf to get rid of this error??

Thanks

[volatile]

Did anyone else working with Chipscope 11.4 had a similar issue?

TIMESPEC TS_J_TO_D: user TIMEGRP 'D_CLK' must be previously defined in FROM/TO constraint

[kellsworth]

I have a similar, but not identical problem with the 11.4 tools and chipscope: 

ERROR:Xst:1396 - Processing TIMESPEC TS_J_CLK: No TNM or User group name J_CLK is defined.

ERROR:Xst:1489 - Constraint annotation failed.

I am integrating an ICON core into my EDK project. I had it working fine, but I generated a new ILA core and now I can't get it to synthesize without that error. 

[ru551n]

Don't want to create a new topic, so I'm posting my solution to the problem here.

Perhaps not related to this problem, but for those with this error message in non-EDK projects, this error is caused if the component declaration (in VHDL) mismatches the one specified in the .vho-file.

[wdsheppard]

I am getting the exact same errors --

ERROR:Xst:1396 - Processing TIMESPEC TS_J_CLK: No TNM or User group name J_CLK is defined.
ERROR:Xst:1489 - Constraint annotation failed.

using Chipscope 13.3.  did you ever get a solution to this problem????

[kevin.moon]

I found this to work:

Under Synthesis options, uncheck Read cores

Under Project options, cleanup project files(this deletes most of the generated files)

Compiles OK now

[kevin.moon]

Update - It seems as if 13.3 has done away with the read cores check box option, so it has to be done as a command line option

on the Other XST Command Line Options add:

-read_cores no

[pepijntje]

Dear Kevin, I'm using EDK 13.3  GUI Windows, where do I have to add your  " -read_cores NO"   ?

[martin@rspsystems.com]

I would also like to know where to  add the  " -read_cores NO"  

[kevin.moon]

It used to be a check box option, but Xilinx dropped that. You need to do it as a command line option

Under Synthesis >> process options ad the following command to "Other XST Command Line Options"

-read_cores no