Design Tools - Others

[weilings]

OK,have you ever use FIFO? I choose the native fifo, common clock,standard mode.And then it comes a question: why the full flag stay high during the rst(asynchronous) is high? and the full flag and the empty flag can stay high at the same time?HELP ME PLEASE! 　ｉｆ　ｙｏｕ　ｗａｎｔ　ｓｅｅ　ｔｈｅ　ｐｉｃｔｕｒｅ　，ｊｕｓｔ　ｌｅａｖｅ　ｔｈｅ　　ｅｍａｉｌ　ａｄｄｒｅｓｓ，Ｉ　ｃａｎ　ｓｅｎｄ　ｙｏｕ　ｔｈｅ　．ｗｃｆｇ．

[eteam00]

Have you read this thread?

-- Bob Elkind

[weilings]

that thread is useless ,it can't solve my problem!

[rcingham]

What FPGA are you targetting?
What versions of ISE and CoreGen?
Are you using behavioural or structural FIFO models?

[weilings]

Vertex-5,
ISE13.3,and the coregen is attached to the ISE 13.3 automatically.
I have tried both behavioral and structural FIFO model,width is 4 and depth is 16.
you can leave your email address ,I can send you all source I have in the project or the picture I got in the form of .wcfg.Thank you very much

[gszakacs]

---

weilings wrote:

that thread is useless ,it can't solve my problem!

---

It isn't clear from your original post just what your problem is.  When I look at the post, the second line

is a bunch of strange hex characters.  The first line describes the expected behavior of a built-in FIFO,

i.e. that the full flag is asserted during reset.  The full and empty flags should never assert together

at any other time.  For FIFO's that don't use the built-in logic, you can select the state of the full flag

during reset.  I believe that the reason for asserting the full flag during reset is to hold off upstream

logic from writing until the reset is complete.

-- Gabor

[weilings]

OK,I repeat the question as follow:

OK,have you ever use FIFO? I choose the native fifo, common clock,standard mode.And then it comes a question: why the full flag stay high during the rst(asynchronous) is high? and the full flag and the empty flag can stay high at the same time?HELP ME PLEASE!  If you want to see my project ,just leave your email address,I can also send you my waveform in .wcfg! you can also send your address to this email box! Thank you very much

[gszakacs]

Yes, I have used FIFO's many times.  I have used the Xilinx CoreGen FIFO's in many projects,

including the built-in FIFO's of the Virtex 5 series.

The Full flag stays high during reset by design.  As I said in my previous post, I believe this

is done so that logic writing to the FIFO holds off until after reset is released.  Obviously no

data can be written into the FIFO while it is held reset.  There is no other independent

"write ready" flag that other logic could use.

For most designs, the reset is only applied at start up, and the state of the full flag at that

time is not important.  If for some reason, you need the full flag to start up low, then you have

the choice of using fabric logic to implement the FIFO (select BLOCK RAM rather than

Built-In FIFO in CoreGen).  Then in another configuration screen you have the option

of selecting the state of the full flag during reset.

The full and empty flags should not be both active at other times besides reset.  It may

take a few edges on the clock before they go inactive after reset, but then you should

never see them assert together.  If you are seeing this, then I would suggest that you

post the simulation waveform here.  You can paste images in the forum post or save

it and attach it as a file.

By the way, I'm still trying to think of why you care about the state of the full flag,

and it occured to me that you may be using it to determine that there is data in

the FIFO (on the read side).  This is wrong.  Only the empty flag (or other programmable

empty / almost empty flags) should be used on the read side.  Only the write

side logic should depend on the full flag (or programmable full / almost full flags).

-- Gabor

[weilings]

yes ,I link the full flag directly to the RD_EN,why can't ?I use common clock . Maybe the function is little different to what I want ,but is the reason why the full flag and empty flag stay high at the same time for about another two clock period after the rst fall back to low ?

[eteam00]

yes ,I link the full flag directly to the RD_EN,why can't ?

You can do this, but it makes little sense.  Why would you wait until the FIFO is completely full before reading from the FIFO?

It makes sense to read data from the FIFO when the FIFO has any data.  This helps keep the FIFO from becoming completely full, and will prevent overrun errors or halted data processing due to a full FIFO.

In your simulation, it does not make sense to assert READ_EN when the FIFO_EMPTY flag is asserted.  Is there a compelling reason for ignoring the FIFO_EMPTY flag in your read logic?

Yes, you can link the FULL flag (but not the EMPTY flag) to your READ logic, and I can tell my wife that I like the way she looks now even more than when she was young and skinny.  Both decisions are a bad idea, however.

-- Bob Elkind