I'm using chipscope in ISE13.2 to debug my design and one of the signals is shown inverted in the chipscope (displays 1 for 0 and 0 for 1)! I triple checked my design and it looks to me that it is getting inverted in chipscope!!
Can you sample it once more and list it twice in the list of signals? Is it possible the signal toogles with the clock and you are a bit too late to get it? Is is possible to register it once more to see the same behavior ?
The signal may have been inverted by the Synthesizer or Mapper to make its life easier. You can stop that happening by adding a 'KEEP' attribute (in the source code).
------------------------------------------ "If it don't work in simulation, it won't work on the board."
